The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A three bit second order delta sigma modulator for audio applications implemented in 130nm CMOS technology is presented. The modulator features two integrators, a flash quantizer and two current steering DACs. In order to minimize the effect of delays in the DACs, excessive loop delay (ELD) compensation is utilized. Using an oversampling ratio (OSR) of 80, the design consumes 2.8mW and achieves a...
Stangenes Industries has developed a solid-state inductor-driven kicker magnet pulse generator for use in a particle accelerator application. The system operates in a neutron environment which precludes the use of standard capacitor-driven systems. A 500–700 A pulse is produced by switching high-current through a large 360 μH inductor from the circuit return into a 6.5 μH kicker magnet. The DC magnetic...
This paper presents several novel low-power low-distortion modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active...
A second-order continuous-time (CT) low-pass ΣΔ modulator using a single feedback digital-to-analog converter (DAC) is presented. To reduce the feedback DACs by one, we introduce half-delayed return-to-zero (HRZ) feedback signaling and feed-forward topology. The HRZ feedback scheme reduces power consumption and die area by removing a summing amplifier and DAC for the excess-loop delay compensation...
This paper presents a novel DC-AC inverter based on a high frequency power electronic transformer. It makes use of an adapted push-pull converter on the primary side of the transformer to apply a high frequency alternating voltage. This keeps the transformer flux low and transformer size small, reducing the cost of materials but at the same time keeping the power density high. The secondary side is...
This paper proposes a fully-distributed GMPLS framework through the use of extended RSVP-TE both for signaling and for routing, modulation and spectrum assignment (RMSA). Our proposed solution achieves lower blocking probability and shorter signaling-latency than does the state-of-the-art GMPLS/PCE architecture.
A low-power low-distortion ΔΣ ADC topology with shifted loop delays is proposed. Compared to the conventional low-distortion modulator, this topology can relax the critical timing for quantization and DEM by shifting the loop delay from the last integrator to the feedback path. Also, by adding one more feedback path, the last integrator can achieve both integration and active summation. Noise-coupled...
Double sampling for delta-sigma ADCs is an effective technique for wideband and low-power data conversion. This paper proposes a double-sampled delta-sigma modulator topology with shifted loop delays. Compared with existing double-sampled modulators, this architecture implements the inherent quantization delay by shifting the delay from the last integrator to the quantizer, and it relaxes critical...
A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a single-amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter...
Finding and comparing power losses in power electronics topologies is most commonly done by using IGBT switching losses from datasheets. The method in this paper, however, is an approach using a measurement setup, of which the data are used in MATLAB Simulink in combination with Plexim PLECS. Using this method, losses are analyzed in T-type, flying-capacitor and diode-clamped multi-level PFC topologies,...
An analysis and synthesis method for continuous-time (CT) band-pass delta-sigma modulators, applicable in parallel converters is presented in this paper. This method makes the design of band-pass delta-sigma modulators possible in a wide range of central frequencies and high DAC+ADC delays. This method is also applicable for narrow-band delta-sigma converters in order to improve their performances.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.