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Soft errors are increasing in modern computers. These faults can corrupt the results of scientific simulations. This work studies error propagation by a bit flip in conjugate gradient (CG) methods. We will also introduce adaptivity to selective reliable fault-tolerant (SRFT) solvers. Our study reduces the compute-intensive reliability steps in SRFT solvers.
Heat generated by electronic devices and circuit must be dissipated to improve reliability and prevent premature failure. Techniques for heat dissipation can include heat sinks and fans for air cooling, and other forms of computer cooling such as liquid cooling. Computer cooling is the process of removing heat from computer components. Because a computer system's components produce large amounts of...
We introduce implementations of arithmetic operators based on the binary stored-carry-or-borrow (BSCB) representation. Several BSCB arithmetic elements, including full-adder, ripple-carry adder, and carry-lookahead adder are presented, followed by detailed design of an array multiplier. In the latter design, the conventional initial AND matrix is transformed and expressed with a redundant radix-2...
With the rapid development of 3G communications, RF circuits are becoming more widespread, so the electronic components VCO's applications grows ever wider, because it is the core module in the oscillator circuit. A voltage-controlled oscillator automatic test system based on GPIB bus is introduced. This system and computer combination has changed the traditional manual operation, VCO production efficiency...
Through tests under Linux operating system, the fact that codes organized differently lead to different temperature of CPU chip was proved. The concept of optimizing codes for chip's reliability is put forwarded. Through tests and examples, a principle and path is proposed, and a few skills for optimizing codes are given.
We are rapidly approaching an inflection point where the conventional target of producing perfect, identical transistors that operate without upset can no longer be maintained while continuing to reduce the energy per operation. With power requirements already limiting chip performance, continuing to demand perfect, upset-free transistors would mean the end of scaling benefits. The big challenges...
Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
Process scaling is well know to increase overall chip-level soft error rates (SER) if no additional mitigation techniques are applied [Seifert04]. The purpose of this study is to summarize recent investigations conducted by the author to characterize the SER benefits and limitations of one particular SER mitigation technique: radiation hardened sequentials that utilize local redundancy. The studied...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
This paper presents an efficient high-level synthesis (HLS) approach to improve RT-level concurrent testing. The proposed method used for both fault detection and fault location. At first the available resources are used in their dead intervals to test active resources for fault detection, and then some changes are applied to the RT-level controller to locate the faults. The fault detection step is...
Built-in self test (BIST) and built-in self repair (BISR) techniques have been developed for memory blocks in recent years. Such techniques are suited to enhance production yield, but also to facilitate long-term dependable circuits though self repair in the field of application. BISR for logic circuits has shown to be much more complex, for which only a few approaches have been published so far....
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
The field of electronic noses and gas sensing has been developing rapidly since the introduction of the silicon based sensors. There are numerous systems that can detect and indicate the level of a specific gas. We introduce here a system that is low power, small and cheap enough to be used in mobile robotic platforms while still being accurate and reliable enough for confident use. The design is...
Scaling in hardware integration process results in IC-process geometry reductions, lower operating voltages and increased clock speeds. This paper first surveys the reliability obstacles these developments give rise to and then points out that computing systems can no longer be safely assumed to fail only by crashing. Yet this assumption is at the core of primary-backup replication which the literature...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
We examine a powerful model of parallel computation: polynomial size threshold circuits of bounded depth (the gates compute threshold functions with polynomial weights). Lower bounds are given to separate polynomial size threshold circuits of depth 2 from polynomial size threshold circuits of depth 3, and from probabilistic polynomial size threshold circuits of depth 2. We also consider circuits of...
A speed independent circuit has the property that the relative speed of operation of the various logic elements does not affect the over-all behavior of the circuit. Such circuits have properties which are of particular importance in the design of reliable asynchronous circuits. An Arithmetic Control for a digital computer is one type of logic which can profitably use these characteristics. The design...
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