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The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without...
This paper represents a method to enhance the linearity of an integrator by implementing feedback compensation topology. The proposed design reduces signal swing while keeping advantages of both feed-forward as well as feedback topology without changing the signal transfer function. Linearity is related to the output of an integrator. Non-linearity resulted because of the integrator's output swing...
In the present paper, an operational amplifier (Op-Amp) topology that achieves high-gain and low-power dissipation is designed and analyzed. The design uses a current mirror with a class-A output stage having capacitive Miller compensation. The low power operational amplifier is the main active power consuming block. The proposed Op-Amp operates at ±0.75V supply voltage and consumes a total...
An operational amplifier is described which uses separate loops to control the output voltage and the error voltage between its inputs. To a large extent this architecture combines the high-speed characteristics of “current feedback” amplifiers with the low input referred errors of precision architectures. The technique has been applied to produce an amplifier with precision characteristics comparable...
This paper presents a lithium-ion battery recharging circuit with an improved charger system topology for portable devices and handheld gadgets. The proposed charger topology uses an operational amplifier with NMOS input for a smooth transition between current control loop and voltage control loop and to control a power pass element device. Using the above-mentioned abilities, a complete charging...
This paper proposes a design for a low power cascaded three stage Operational Amplifier, with frequency compensation by Nested Miller Compensation which could be made to operate at low voltage supplies. The multipath technique is used to increase the bandwidth by converting the system into a two stage amplifier at high frequencies. The Op-Amp is designed in 180 nm technology and operates at a 3 V...
A 12 bit 50 MS/s 1.8 V pipelined CMOS analog-to-digital converter (ADC) based on a fully differential class-AB switched operational amplifier achieves low power consumption with a differential input voltage of 2.4 Vp-p. A global-loop dynamic common-mode feedback circuit enables fully differential class-AB operation with dynamic current switching for power reduction. The prototype ADC shows a peak...
A new Current Feedback Amplifier (CFA) suitable for VLSI applications is presented in two different designs to serve both low power (LBW design) and high bandwidth (HBW) applications. The new circuit is employing positive current conveyor followed by amplifier followed by buffer to achieve very high trans-impedance for this CFA circuit without needing to stack many transistors together and at the...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topology generation. A new kind of GA is developed, where a fraction of the offsprings in each generation is built from building blocks or cells obtained from previous generations. The cells are stored in a hierarchically arranged...
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