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The main requirement of Very Large Scale Integration (VLSI) circuit is to be fast and low energy consumption. So, the analysis is done by optimizing the delay, which results in fast processing and low average energy consumed. A 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 90 nm technology. The results from...
This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor...
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed...
The Ex-OR and Ex-NOR gates are the basic building blocks of various digital system applications like adder, comparator, and parity generator/checker and encryption processor. This paper proposes a full swing pass transistor based Ex-OR/Ex-NOR gate which gives better driving capability, less propagation delay and low power dissipation as compared to the existing Ex-ORlEx-NOR circuits, and by modifying...
A new low power dynamic CMOS one bit full adder cell is presented. In this design technique is based on semi-domino logic. This new cell is compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay-product and leakage performance of low voltage full adder cells in different CMOS logic...
This paper proposes a Low-Power, Energy Efficient 4bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth) scheme has been introduced while designing the full adder blocks to reduce the Leakage Power, as well as, to maintain the overall performance of the entire circuit...
In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency. In...
This paper investigates a robust 1-bit static full adder using FinFET at near-threshold region (NTR), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region provides minimum-energy point for the different frequency of operation with more favorable performance and variability characteristics. The proposed design features higher computing...
In this paper the most interesting topologies of one-bit hybrid full adders, are analyzed and compared for speed, power consumption, and power-delay product. The investigation has been carried out with properly defined simulation set up and input pattern on a Mentor Graphics environment using a TSMC 180 nm CMOS process. Performance has been also compared for different supply voltage values. The simulation...
Full adder is an essential component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors etc. Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance...
A new low power and high speed full adder is designed which targets at tree structured applications. By employing complementary signal at input, buffer inverter at output, a new transmission gate based full adder is proposed. This new adder uses 20 transistors to achieve high driving ability and low power consumption. Simulation in Semiconductor Manufacturing International Corporation 0.18-μm CMOS...
This paper presents an improved circuit design of low power 1-bit full adder circuit. The circuit is designed and implemented based on top-down approach using total number of 10 transistors, thereby, known as 10-T cell. After simulation of the circuit, a clear view of the circuit performance, in terms of power, delay, area was studied. The performance of the proposed circuit was compared with other...
Optimization of power and delay is very important issue in low-voltage and low-power applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors and low-threshold to some others. Here, the polarity of the MOSFETs is considered as the selection criteria for assigning threshold. In order to achieve the best leakage...
In this paper a new high speed and low power adder is presented. The circuit uses a hybrid concept of analog and digital circuit design to propagate the carry and so achieve a Full Adder with 78 ps delay and 7.26 muW of power consumption. SPICE Simulations performed on the 0.18 mum TSMC Technology demonstrates the average improvement of 159%, 184% and 516%, respectively for delay, power consumption...
This paper presents a high performance 16times16 bit 2's complement multiplier using MOS current mode logic (MCML). A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, MUX and full adder are designed and optimized for low power and high-speed operation. Using these gates, a 16 bit MCML signed multiplier is designed and tested for 4 different supply current, in a UMC 0.18 mum CMOS...
This paper proposes four low power adder cells using different XOR and XNOR gate architectures. Two sets of circuit designs are presented. One implements full adders with 3 transistors (3-T) XOR and XNOR gates. The other applies Gate-Diffusion-Input (GDI) technique to full adders. Simulations are performed by using Hspice based on 180 nm CMOS technology. In comparison with Static Energy Recovery Full...
A full adder circuit is one of the basic building blocks of a digital design. In general it is made by CMOS technology. In the CMOS technology the full adder is built by 28 transistors. So, the transistor count is very high. The average power consumption, leakage power consumption and delay is very high. In this paper we made a new circuit which is made by mainly the transmission gate (TG) technology...
In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation results show a 5%-20% for frequency ranges from 1 KHz to 20 MHz and supply voltages lower than 0.3 V.
The paper presents a novel high speed and low power 15-4 Compressor for high speed and low power multiplication applications. The proposed compressor uses bit sliced adder architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed compressor is also centered around the design of a novel 5-3 compressor that attempts to minimize the stage...
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