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This paper investigates a robust 1-bit static full adder using FinFET at near-threshold region (NTR), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region provides minimum-energy point for the different frequency of operation with more favorable performance and variability characteristics. The proposed design features higher computing...
As technology is scaling down, circuit reliability issues are major concerns because digital circuits are more susceptible to external noise sources. Soft Error is one such source which changes the voltage of internal nodes of the circuit. Hence it is necessary to design soft error (SE) immune digital circuits. In this paper, we proposed a novel SE immune latch circuit which operates at 0.5V using...
As CMOS technology is scaled down, the supply voltage and gate capacitance are reduced, which results in the reduction of charge storing capacity at each node and increase of the susceptibility to external noise in radiation environments. In this paper, a novel hardened latch design is proposed and compared with the previous hardened latch designs using 32nm technology node. Extensive simulation results...
Optimization of power and speed is a very important issue in low-voltage and low-power applications. In this paper, a 1-bit full adder cell has been successfully analyzed by assigning high-threshold voltage to some transistors and low-threshold voltage to others. Moreover, a robust full adder circuit using dual threshold voltage MOSFETs (DT-MOS) has been proposed. The proposed design features lower...
Leakage is a growing issue with the advancements of technologies. It is a predominant problem of on chip caches of microprocessors. The cache is a major portion of the microprocessor area. Further, the SRAM cell is a significant contributor of transistor leakage power. This paper analyses leakage-delay trade-off for increase of the transistor gate length in the on chip cache at 22nm, 32nm and 45nm...
Subthreshold design has been proposed in the literature as an effective technique for designing signal processing circuits needed in wireless body area network (WBAN) powered by sources with limited energy. The full adder cell forms the basic building block of majority of these signal processing circuits. In this paper, 8-Bit subthreshold Ripple Carry Adders (RCAs) for wireless sensor nodes optimized...
Tolerance to soft errors has become a strict requirement in today's nanoscale CMOS designs. This paper proposes a new hardening design technique for CMOS memory cell at 32nm feature size. The proposed hardened memory cell overcomes the problems associated with the previous designs by utilizing novel access and refreshing mechanisms. Simulation shows that the data stored in the proposed hardened memory...
This paper presents a comparative study of two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 5 times larger tolerance to Vth and L mismatch...
Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as major challenges in ITRS. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variation in sense amplifiers lead to significant loss of yield. In this paper, we present a process variation tolerant self-compensating...
NBTI imposes a challenge for the design of circuits in DSM technologies. NBTI causes increase of Vt of the PMOS transistors, thus leading to timing degradation of CMOS circuits over time. This manuscript presents a NBTI-aware transistor sizing technique for high-performance CMOS gates, which improves the cell reliability with minimum area penalty. The delay of an inverter designed on a 32 nm technology...
This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 mV.um) and low 1/f noise...
A variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed in this paper for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate...
Intrinsic MOSFET time delay is examined as a function of scaling of high-performance CMOS technology. An analytical expression is used to calculate delay from physically meaningful transistor characteristics, which are either obtained from the literature or projected forward. The key performance parameter is the calculated virtual-source carrier velocity in the channel which is shown to be responsible...
In this paper, a low power and low jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The CMOS DCO design is based on a ring oscillator implemented with Schmitt trigger based inverters. Simulations of the proposed DCO using 32 nm predictive transistor model (PTM) achieve controllable frequency range of around 570 MHz~850 MHz with a wide range of linearity. Monte Carlo simulation...
In this paper, a low power and low jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The CMOS DCO is designed based on a ring oscillator implemented with Schmitt trigger based inverters. Simulations of the proposed DCO using 32 nm CMOS predictive transistor model (PTM) achieves controllable frequency range of 570 MHz~850 MHz with a wide linearity. Monte Carlo simulation...
Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation ULSI circuits. In this paper we propose a high performance voltage sense amplifier in sub 32-nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed design improves the sensing delay and shows excellent tolerance to threshold voltage mismatch...
The outlook of performance scaling in high-performance CMOS is explored by using an analytical expression for the intrinsic MOSFET delay. The historical trend of carrier virtual source velocity, as the main driver for continuous performance increase in the past, is presented and prospects of further velocity increase in future technology nodes are discussed. An optimistic scaling scenario with realistic...
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
This study investigates key elements improving CMOS critical path speed. We proposed a full analysis of input signal slope impact on the switching current trajectories depending on Vt centering. Based on inverter output characteristics shape, we demonstrated that speed of low-Vt (LVT) path preferred higher drive current (ION) whereas high-Vt (HVT) cells speed is enhanced by lower drain induced barrier...
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