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The clock distribution is important in all synchronous VLSI Design. The clock skew impacts the performance of synchronous logic circuits. As the scaling moves to nanometer technology, innovative clocking techniques are required to optimize the skew. This is done in backend process of design flow, (i.e.) skew is optimized in Pre and Post CTS. Here tunable clock buffers and tunable clock inverters is...
Current VLSI systems-on-Chips (SoCs) integrate billions of transistors and are clocked with multi-gigahertz clock frequencies. As the geometrical dimensions of both devices and wires in theses systems become smaller, the internal communication performance between the SoC's blocks is heavily affected by the on-chip interconnect wire delays. In this paper, we propose a high efficient mesochronous outfit...
The interest in non-synchronous design of digital circuits is growing due to technology scaling into deep submicron transistor geometries and to the problems this scaling causes to keep synchronous design advantageous. To enable most non-synchronous styles, the C-element is a fundamental device that has to be available as logic primitive. A recently proposed design flow improved a standard cell library,...
This paper presents a new voltage controlled delay line (VCDL) for a 30-phase 500MHz DLL. The new VCDL circuit solves the problem of flicker noise caused by the tail current source. The post-simulation result indicates that the VCDL has moderate linearity range, low Processing-Voltage-Temperature (PVT) sensitivity and good noise resistance. It can be perfectly applied in the 5Gbps Over-sampling based...
Today, a great concern for the integration of high-frequency systems are the problems associated with the synchronization difficulties. The VCO block of PLLs is the primary source of timing jitter and this work addresses issues significant to the design of VCOs with Single-Ended Control in PLLs. The main goal of this work is to develop Two high frequency CMOS PLLs in 0.13μm technology. The advantage...
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity, 2) combined implementation of the functional and completion detection logics, what simplifies the design process, 3) circuit output latency is based on the actual gate delays of the unbounded nature, 4) absence of additional synchronization chains...
The C-element is a fundamental component in asynchronous circuits and quite used in synchronous circuits to mitigate transient faults. This work evaluates the transient-fault effects on the traditional dynamic, conventional, weak feedback, and symmetric C-element's implementations. An evaluation methodology is developed by means of fault-injection simulations at transistor level. Unlike existing methods,...
In this paper, a new wave-pipelining scheme is proposed. In classical wave-pipelining scheme, the data waves propagate on the circuit and the propagating waves are sampled simultaneously when they reach to a synchronization stage. In this new wave-pipelining scheme, only the components of the wave whose delay-difference values reach to a critical value are sampled. Other components, which are not...
Clock Gating (CG) is a well known technique to reduce dynamic power consumption by stopping the clock to avoid unnecessary transitions in synchronous circuits. The abilities of different CG-styles to save power at a flip-flop level, depending on the input activity, are analysed in this paper. Also, since conventional CG techniques usually do not take into account leakage power, some optimization procedures...
Current Sensing Completion Detection (CSCD) method in asynchronous circuits is addressed. Current Sensing represents a simple but effective and reliable approach to detect completion of computation in asynchronous (self-timed) systems. However, in recent deep sub-micron technologies, several challenges, such as significant influence of process variations, leakage current power dissipation with circuit...
Flip flops used to store a bit in a register have different requirements to flip flops used in a synchronizer application. The D input must be held stable during the setup and until the Q output appears, these times determine the remaining part of the clock cycle available for computing. On the other hand the D input can violate setup and hold times in a synchronizer, and the reliability of the synchronizer...
In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop. The ULV flip-flop offers increased speed compared to other FF's for low supply voltages. The pulse generator (PG) circuit in a conventional sense amplifier SAFF is replaced by a high-speed tristate edge generator (EG) with a rise- and fall-time less than 1/10 of an inverter operating with the same supply voltage. In essence the...
In this paper we examine a quasi static and a static ultra low-voltage precharge CMOS logic. The static ultra low-voltage logic can be used to design high speed and energy efficient CMOS circuits. Using the proposed circuit technique the static current consumption can controlled and the logic style is suitable for large logic depth, i.e. serial adders. The delay of a static ultra low-voltage gate...
A novel GALS (globally asynchronous locally synchronous) asynchronous communication circuit which adopts the single-track handshake protocol is proposed. The circuit can complete data transmissions without acknowledgement signals. The backward transition of the circuit becomes delay-insensitive by adding an NCL (null convention logic) threshold gate in the RTZ (return to zero) process. The circuit...
As CMOS technology enters sub-micron era, a large number of intelligent properties (IPs) are integrated on a single chip (SoC). The communication patterns become difficult to model. At the same time, as transistors become small and wires become narrow, delays are becoming more and more unpredictable. The factors greatly challenge traditional on-chip buses and point-to-point interconnects because of...
Aggressive technology scaling tends to reduce integrated circuits resilience against environmental variations. In this paper, we present an adaptive clock buffer circuit design and an adaptive clock distribution network (CDN) to improve chip performance and reliability in the presence of on-chip power-supply variations. The adaptive buffer provides a supply insensitive propagation delay to minimize...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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