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By introducing a signed-digit (SD) number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a high-speed modulo m SD addition algorithm is proposed, where m\in \{2^n-1, 2^n+1, 2^{2n}+1, 2^n\}. By using the modulo m SD adders, a modulo m SD multiplier can be implemented with a binary adder tree structure. We also present an algorithm for...
The hardware implementations of decimal arithmetic operations, which are commonly used in financial, scientific, and internet-based applications requiring accuracy and speed, become prominent. In this paper we first analyze the column sum boundaries of n-digit parallel decimal array multipliers (PDAM). A general form of the problem is formed and a heuristic solution is found with Genetic Algorithm...
A new technique for addition and subtraction of two digital signals is presented and implemented in FPGAs. The proposed technique is based upon the representation of signals as a Walsh series. A spectrum is generated which can be used for analysis and processing of digital signals directly. The results of addition and subtraction of two digital signals, represented as 8-bits signed number with 16...
Fast multiplication can be achieved by using canonical signed digit (CSD) to speed-up computations. Conversion to CSD is needed when the multiplier is not known a priori. In this work, a novel approach for converting an unsigned binary number or two's complement number to its CSD form from least significant bit to most significant bit, (right-to-left), is presented. Comparison shows that our algorithm...
In this paper, we propose a high-performance logarithmic converter using novel two-region bit-level manipulation schemes. The proposed technique provides an area-time-efficient hardware implementation, since it avoids the need of a ROM by using simple arithmetic operations instead. Accuracy analysis shows that the proposed converter can achieve an error range and percent error range of only 0.0319...
While scan-based compression is widely utilized in order to alleviate the test time and data volume problems, the overall compression level is dictated not only by the chain to channel ratio but also the ratio of encodable patterns. Aggressively increasing the number of scan chains in an effort to raise the compression levels may reduce the ratio of encodable patterns, degrading the overall compression...
A method for speed increasing in arithmetic circuits such as addition, subtraction and multiplication, is the Residue Number System (RNS). The absence of carry, realization of high-speed and low-power arithmetic and more security are some advantages of RNS. One-Hot is a way for RNS performance. In One-Hot Residue Number System (OHRNS), We define M module by M-bits. The big number of pass transistors...
Hardware realization of decimal arithmetic operations is becoming a necessity in commercial, financial and internet-based applications. Exponentiation is a frequently used but time-consuming operation for these applications. Usually, squaring and multiplication are combinedly used to simplify exponentiation. Though research in decimal multiplication has received a lot of attention, the exploration...
In this paper, we present multipliers using a modified binary tree of the modulo m signed-digit (SD) number residue adders where m=2n-1, 2n, 2n+1. New additions rules are used for generating the intermediate sum and carry with a binary number representation. The sums and carries are directly inputted into the next stage of adders, so that the modulo m multiplier using binary modulo m adder tree proposed...
The moduli set {2n-1, 2n, 2n+1, 22n+1-1} has been newly introduced for residue number system (RNS) as an arithmetic-friendly large dynamic range moduli set which can lead to a fast RNS arithmetic unit. In this paper, we present a reverse converter for the moduli set {2n-1, 2n+1, 22n, 22n+1-1} which is derived from the moduli set {2n-1, 2n, 2n+1, 22n+1-1} by enhancing modulo 2n to 22n. With this enhancement...
The paper presents a novel method for constructing soft servo networked motion control system via EtherCAT network. The EtherCAT network performance is analyzed in detail through comparison of it by other several industry Ethernet protocols. We give out the application PLC program flow chart of synchronous control. The experiment results show that the soft servo networked motion control system can...
This paper presents a new residue number system (RNS) to binary converter for the novel four-moduli set {2n/2 -1, 2n/2 +1, 2n +1, 22n+1 -1} for even n, based on new Chinese remainder theorem 1 (New CRT-I). Due to the simple multiplicative inverses of the proposed moduli set, it can considerably reduce the complexity of the RNS to binary converter. The presented converter architecture is adder-based,...
Residue number system (RNS) is an appropriate system for fast and parallel arithmetic operation. This speed increases if one-hot residue (OHR) number system is used. There are problems in OHR with area and hardware consumption, when modules are large or result of various arithmetic operations is needed. In this paper, a new design for concurrent add and subtract operation in OHR systems, using barrel...
Leading Zero Anticipator (LZA) is a technique to calculate the number of leading zeros of the result in parallel with the addition. General algorithms can work effectively for a subtraction, and obtain the leading one position from exponents of operands for an addition or a multiply-add-fused (MAF) operation. However, using exponents to get leading zero number can introduce another error of one bit...
In this paper, the working principle of reflective memory network is introduced, reflective memory network is designed and realized, and real-time, delay determinacy and reliability of reflective memory network are tested under QNX real-time operating system. The performance tests indicate that the reflective memory network meets the demands of the real-time and dependability and improves the stability...
This paper focuses on problems of the end to end voice quality assessment. Up to now there have been developed lot of measuring methods, which objectively determine final quality of transmission. This paper deals with the PESQ (Perceptual Evaluation of Speech) algorithm described in the ITU-T P.862 and its use. The basic intent of this work was to develop a device which is able to measure voice transmission...
RSA encryption is one of the public-key methods that has been popular in last decade. Considering increment of security requirements, size of the keys has been larger. With key length growing, delay of exponentiation computation has changed into major problem in selecting longer keys. The binary or in other words square-and-multiply method is the classical exponentiation technique that is used in...
Parallel design and realization of artificial neutral networks on clusters can fully employ the advantage of ANN parallel processing, shorten the training time and reduce the algorithm complexity. As the parallel techniques become more and more developed, it's increasingly important to design artificial neutral networks on clusters via a combined software and hardware method. The support of parallel...
Datapath merging is an efficient high level synthesis method to merge data flow graphs (DFGs), corresponding to two or more computational intensive loops. This process creates a general purpose datapaths (merged datapaths) instead of multiple datapaths that results in shorter bit-stream length and therefore reduces the configuration time in reconfigurable systems. The merged datapath, however has...
In this paper, we present the hardware design of a combined decimal and binary floating-point divider, based on specifications in the IEEE 754-2008 Standard for Floating-point Arithmetic. In contrast to most recent decimal divider designs, which are based on the Binary Coded Decimal (BCD) encoding, our divider operates on either 64-bit binary encoded decimal floating-point (DFP) numbers or 64-bit...
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