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Embedded scan test compression is used to enable high test quality and has become a standard practice on many designs. This paper describes power and timing experiences related to embedded compression technology. A commercial tool was used to implement EDT compression technology in three wireless designs. The case study and results demonstrate the effect of power reduction methods and timing closure...
This paper deals with the problem of identifying a Petri net system given an observed sequence of events generated by it and an observed sequence of output vectors associated to the marking of the measurable places. The problem is not new in the literature. The original contribution of this work consists in the use of the timing information associated to the net so as to improve its identification...
In this paper, a novel optimum data-aided timing offset estimator that only relies on symbol-rate samples for frame-level timing acquisition is derived based on the maximum likelihood criterion. For this purpose, we exploit the statistical properties of the power delay profile of the received signals to design a set of the templates to ensure the effective multipath energy capture at any time. We...
Coordinated Multi-Point transmission / reception (CoMP) has been adopted in LTE-Advanced to improve system performance, especially user equipment (UE) at the cell edge. The conventional timing advance (TA) design is not suitable since a UE can be served by multiple geographically distributed access points (AP). TA issue's impact is investigated in great detail. Simulation results validates that the...
Based on the analysis for the requirement of the Field-Programmable Gate Array (FPGA) when the time interpolation time-to-digital converter (TDC) is planed to be applied in it, this paper describes a double sampling architecture for time interpolation TDC in the FPGA. The architecture extends the cover range of the delay-chain for twice, and can be implanted in those low-cost limited logic density...
Testing for small delay defects is critical to guarantee that the manufactured silicon is timing-related defect free and to reduce quality loss associated with delay defects. Commercial solutions available for testing of small delay defects result in very high pattern count and run time. In this paper, we present two effective approaches for generating timing-aware transition fault patterns that target...
We investigate the influence of a realistic supply voltage network on the timing margins for a commercially-available 32-bit processor chip. Detailed models of the supply network and switching activity produce a spatial map of the supply voltage waveforms. We relate these waveforms to the expected excess logic delays, and estimate the required derating of the critical setup paths.
Signal control based on bus priority is an important and economical way to implement the measures of bus priority. Among many kinds of methods of signal timing, this paper chooses the WEBSTER method. The bus priority signal timing program is based on the minimum of the total delay of the passengers, which is regarded as an optimal aim of cycle and green time. Compared with the average vehicle delay...
As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and decentralized round-robin arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters,...
As Globally Asynchronous Locally Synchronous (GALS) systems are becoming preponderant in complex SoC and NoC, we present the design and implementation of a new GALS adapter to be used in ANoC, an asynchronous NoC architecture. The proposed GALS adapter is a complete IP integration module, including a new FIFO based design using a Johnson-encoding principle for timing domains interfacing, and a local...
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outputs...
The long term evolution (LTE) of 3GPP radio-access technology aims to develop a framework towards a high-data-rate, low-latency and packet-optimized radio access technology: Evolved Universal Terrestrial Radio Access Networks (E-UTRAN). However, low terminal transmission power, short TTI length and long HARQ RTT give a critical problem on LTE TDD UL performance in a coverage-limited scenario. To solve...
Limited transmission power and short TTI length impose a bottleneck on LTE UL performance in a coverage-limited scenario. This paper presents an effective coverage enhancement mechanism called TTI bundling to boost uplink VoIP performance in LTE FDD mode. Performance evaluation for TTI bundling with VoIP traffic is carried out by semi-static system simulation, and the impact from different bundling...
One of the biggest challenges in ultra-wideband impulse radio (UWB-IR) is timing acquisition. To accomplish synchronization, a novel modulation scheme is presented in this paper. Relying on the unique signal structure and the first order- statistics of the received signal, the timing offset can be acquired by energy detection even if in the presence of inter-frame interference (IFI) and inter-symbol...
Timed model-based testing is a technique which allows for the specification of timing in the model as well as in the test cases. As such, it is well suited for the testing of embedded systems, which usually puts a much higher demand on the amount of test cases and quality of the test process than other software systems do. While the theory of timed testing is well established over the last years,...
As semiconductor technologies are aggressively advanced, the problem of parameter variations is emerging. Process variations in transistors affect circuit delay, resulting in serious yield loss. Considering the situations, variationaware designs for yield enhancement interest researchers. This paper investigates to exploit the statistical features in circuit delay and to cascade dependent instructions...
Derating is a versatile technique supported by all static timing analysis (STA) tools in industry. In essence, it enables designers to modify any delay or slew computation performed by such tools. Despite this common use in industry, the scientific literature on derating is scarce to none. This has led to its incorrect use, misunderstanding, and even dismissal. This situation has also been exacerbated...
Commercial crosstalk analysis tools are widely used for timing verification of LSI, but they analyze the worst case of crosstalk effect in any theoretical cases, which is really pessimistic. Some works have been done to reduce the pessimism based on deterministic method like logical correlation or timing window correlation. In this paper, a novel and practical crosstalk analysis introducing probability...
In this paper we propose a technique to determine accurate interconnect extraction corners for a 65-nm design using parametric RC extraction and timing analysis. We calculate the sensitivity of a design metric such as hold slack to each interconnect variation parameter. These sensitivities are then sorted for a selected number of critical paths. Finally, we utilize this information to determine the...
This paper discusses the network covert timing channel. This channel modulates network packet's time properties to transfer information secretly. Much work has been done in inventing and utilizing network covert timing channels, however, there is not so much work in other areas such as detecting and handling covert channels. Covert channel detection is difficult, what's more, it often needs human...
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