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Designs with non-tree consideration have been proven to improve the yield and reliability in modern chips. In this paper, an efficient three-phase approach for transformation-based timing analysis is proposed to transform a cyclic graph into an acyclic graph by using the node-splitting operation and compute the delay of the transformed tree-based circuit in an Elmore delay model. Compared with the...
Transistor aging results in circuit delay degradation over time,and is a growing concern for future systems. On-line circuit failure prediction, together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing. Effective circuit failure prediction requires very thorough testing to estimate the amount of aging in various parts of a large design...
The trends in technology scaling have made nanometer designs highly susceptible to reliability threats like soft errors and crosstalk noise while uncertainty in process parameters have made the physical realization of devices and interconnects unpredictable. The limitations in manufacturing processes and the impact of environmental noise poses a major threat to the signal quality, and hence the realization...
Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and significant parametric variations. Asynchronous circuits have the great potential to achieve delay insensitive, high performance and low power nanoelectronic design, while the existing asynchronous circuits do not guarantee logic and timing...
Today's process technologies place emphasis on low power design in multi-core systems that require the complicate communication networks-on-chip (NoC) architecture to be reliable. Considering the many error control codes (ECCs) implemented in a hardware NoC router, the primary objective of this paper is accounting for the causes of energy consumed for fault tolerance and providing a way of comparison...
As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, reducing leakage power remains to be one of the design goals. Because both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input vectors, Input Vector Control (IVC) technique may be...
Optical shrink for process migration, manufacturing process variation, temperature and voltage changes lead to clock skew as well as path delay variations in a manufactured chip. Such variations end up degrading the performance of manufactured chips. Since, such variations are hard to predict in pre-silicon phase, tunable clock buffers have been used in several designs. These buffers are tuned to...
Process and environmental variations continue to present significant challenges to designers of high-performance integrated circuits. In the past few years, while much research has been aimed at handling parameter variations as part of timing analysis, few proposals have actually included ways to interpret the results of this parameterized static timing analysis (PSTA) step. In this paper, we propose...
Degradation of device parameters over the lifetime of a system is emerging as a significant threat to system reliability. Among the aging mechanisms, wearout resulting from NBTI is of particular concern in deep submicron technology generations. To facilitate architectural level aging analysis, a tool capable of evaluating NBTI vulnerabilities early in the design cycle has been developed. The tool...
This paper presents a novel path selection methodology to select paths for monitoring unexpected systematic timing effects. The methodology consists of three components: path filtering, path encoding, and path clustering. Given a large set of critical paths, in path filtering, the goal is to filter out paths that cannot be functionally sensitized. To explore the space of unexpected timing effects,...
With nanometer processes, at-speed testing is required to filter out failing chips with delay defects to ensure high product quality. Locating delay defects is important not only for improving yield but also providing important information to enhance at-speed test methods to meet quality goals. In this paper, a method that leverages successful static defect diagnosis method to diagnose delay defects...
An efficient crosstalk delay degradation measurement method with a 65 nm process is proposed. The voltage drop impact on the crosstalk delay is measured. The test module incorporates filters which omit glitches high speed complicated circuits unintentionally create. The module consists of standard cells only, that makes designing very easy. An intensive comparison of measured results with simulations...
Unintentional clock skew caused by variability can result in degraded and unreliable system performance. In this paper, we present a deskewing technique that continuously senses and compensates for unintentional clock skew. It uses an enhanced skew detector block that detects the skew magnitude in addition to the phase. This helps eliminate the need for complex feedback control, thus reducing the...
Aggressive technology scaling tends to reduce integrated circuits resilience against environmental variations. In this paper, we present an adaptive clock buffer circuit design and an adaptive clock distribution network (CDN) to improve chip performance and reliability in the presence of on-chip power-supply variations. The adaptive buffer provides a supply insensitive propagation delay to minimize...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises superiority in exploring the flexibility offered by a design over all previous representation methods. In this work, we illustrate how the SPFD of a particular wire reveals information regarding the number of potential transient...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
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