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Atomicity races in ARINC 653 applications are a kind of concurrency bugs which causes nondeterministic behaviors by parallel processes. This paper presents a tool, called AR653, to dynamically detect atomicity races. The tool monitors only synchronization operations and access to shared resources, and analyzes the relation of synchronizations to report atomicity races through a locking discipline...
We study whether local structural changes in a complex network can be distinguished from passive remote time-course measurements of the network's dynamics. Specifically the detection of link failures in a network synchronization process from noisy measurements at a single network component is considered. By phrasing the detection task as a Maximum A Posteriori Probability hypothesis testing problem,...
A non-blocking implementation of a concurrent object is an implementation that does not prevent concurrent accesses to the internal representation of the object, while guaranteeing the deadlock-freedom progress condition without using locks. Considering a failure free context, G. Taubenfeld has introduced (DISC 2013) a simple modular approach, captured under a new problem called the it fair synchronization...
SCADA is widely used in critical infrastructures for monitoring and controlling the processes of industrial plants. The communications that occur in SCADA systems are transmission of sensed real time data across various devices, details of activities going on in the devices, information related to breaks and leakages in the system etc. As the numbers of deliberate cyber attacks on these systems are...
We study the detection of link failures in network synchronization processes. In particular, for a canonical linear network synchronization model, we consider detection of a critical link's failure by a monitor that makes noisy local measurements of the process. We characterize Maximum A-Posteriori (MAP) detection of the link failure, for both the case that the monitor has information about the network's...
Zero-Degree Detector (ZDD) is a new Detector of Beijing Electron Spectrometer III (BESIII) for both double gamma event detection and luminosity monitoring to substitute the old luminosity monitor. A new luminosity readout is described in this paper which is designed in double width AMC/MTCA form factor with a large Xilinx Virtex5 FPGA in addition to normal electronic signal formation. A FPGA embedded...
Today's distributed real-time systems require flexibility to adapt to evolving functional and non-functional requirements in run-time. The authors have presented in previous works a middleware architecture based on the Flexible Time-Triggered (FTT) paradigm that allows creating flexible real-time distributed applications over CORBA. This paper focuses on the design of the central node of the architecture,...
The open-loop de-skewing circuits are traditionally used for fast clock synchronization, but they are unable to deal with the problems induced by run-time variations. This paper presents the design of a skew compensation circuit that can achieve fast lock-in and also perform maintenance operation after lock-in. This circuit is designed on top of the open-loop half-delay-line skew compensation circuit...
Multithreading and concurrency are core features of the Java language. However, writing a correct concurrent program is notoriously difficult and error prone. Therefore, developing effective techniques to find concurrency bugs is very important. Existing static analysis techniques for finding concurrency bugs either sacrifice precision for performance, leading to many false positives, or require sophisticated...
ATLAS is one of the two general-purpose detectors at the Large Hadron Collider (LHC). Its trigger system must reduce the anticipated proton collision rate of up to 40 MHz to a recordable event rate of 100-200 Hz. This is realized through a multi-level trigger system. The first-level trigger is implemented with custom-built electronics and makes an initial selection which reduces the rate to less than...
The LHCb experiment is a hadronic precision experiment at the LHC accelerator aimed at mainly studying b-physics by profiting from the large b-anti-b-production at LHC. The challenge of high trigger efficiency has driven the choice of a readout architecture allowing the main event filtering to be performed by a software trigger with access to all detector information on a processing farm based on...
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high bandwidth (2.16 Tbit/s), low latency, and flexibility in the processing algorithm. The input data come optically via 1 080 links operating at 2.5 Gbit/s. The whole system is partitioned hierarchically in 18 groups of 5+1 modules...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A system for the interrogation of fiber Bragg grating (FBG) sensors using a strain-tuned EDF laser with linear cavity is described. An optical switch is spliced to one end of the laser cavity and connects one of two high-strength draw-tower fiber Bragg gratings (DTGs). The gratings are simultaneously tuned by a stretching device and act as the end reflector of the laser cavity. By applying a ramp...
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