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A new switch control method for a capacitive DAC architecture has been presented. This has been implemented to make a successive approximation register (SAR) ADC more energy efficient. By splitting the capacitor array into two equal halves and using a unity gain buffer, the proposed architecture reduces the switching energy by 97 percent compared to the conventional switching method. The proposed...
A wideband LC voltage-control oscillator (VCO) is designed based on SMIC 0.18μm CMOS process, which has wide tuning range by using the switched capacitor array, while the phase noise is reduced after using the differential inductance of high quality factor and the filter method. Simulated results show that the VCO has the tuning range of 23.3% from 2.12GHz to 2.68GHz, and the phase noise of -128.1dBc/Hz...
A biomedical electronics interface to detect heart signals is presented including a reconflgurable full differential fifth-order Bessel Gm-C filter and a 12 bit low-power fully differential successive approximation register analog-to-digital converter (SAR ADC). The total fully differential structure reduces the input signal noise and distortion effectively. A switch array is used in Gm-C filter to...
Based on TSMC 0.18μm 1P6M RF CMOS process, a 4th-order Butterworth analog low-pass filter (LPF) used in the transmitting link of 2.4GHz Wireless Sensor Network (WSN) radio frequency (RF) front-end is designed in this paper. In this design, active-gm-RC structure is derived, and it can achieve the same low consumption performance as the gm-C structure while have better linearity than that of the gm...
This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.
A novel characterization setup for integrated capacitor array mismatch determination is presented. The biasing of twenty capacitor units and the selection of a specific array are controlled by externally generated digital signals. Information about the spatial matching behavior is provided for an entire MIM capacitor array, where the relevant parameters are the standard deviations ??(??Ci / C) and...
An autofocus (AF) sensor with global shutters using offset-free frame memory is presented. A cross-shaped AF sensor array has left and right horizontal arrays and top and bottom vertical arrays. AF is achieved by calculating the phase difference from the digital code of the light illumination difference between the left and right (or top and bottom) arrays. The global shutter was implemented by using...
A new current mirror based all-pass, tunable phase shifting technique is proposed and simulated in 0.18 um CMOS, after a brief introduction on phase shifter applications, and comparison between different implementation methods. In the new current-mode approach, cut-off frequency of transistor is the operational limit of the proposed phase-shifter architecture and power consumption for this design...
A new current mirror based all-pass, tunable phase shifter architecture is proposed in 0.18 um CMOS, after a brief introduction on phase shifter applications, and comparison between different implementation methods. In the new current-mode approach the cut-off frequency of transistor is the operational limit of the proposed phase-shifter architecture and power consumption for this design is 80 microwatts...
A successive approximation ADC based on the C2C DAC architecture is introduced. The ADC designed in a 0.18 ??m CMOS 2 Poly 4 Metal process uses a hybrid capacitive DAC combining the best of the binary weighted capacitive array and the C2C array. C2C ladder based architectures are very attractive for implementation because of its small area, high speed and low power consumption. However a major drawback...
Digitally controlled oscillator (DCO) for digital audio broadcasting (DAB) is proposed using 0.18 ??m CMOS process parameters with 1.8 V supply voltage. In this paper, the proposed DCO consist of tri-state inverter array and calibration block. Tri-state inverter array is 5-stage ring oscillator and each stage has 160 tri-state inverters. Calibration block is composed of 64 NMOS pass transistors and...
In this paper a 12 bits 50 kS/s micropower hybrid ADC is proposed for biomimetic microelectronic systems using 0.18 mum CMOS process. The hybrid ADC combines SAR and dual-slope architectures to achieve 12 bits, power consumption 60 muW, and small silicon die size. This hybrid ADC shows very good figure-of-merits (FOM) on both power consumption and silicon die size compared with conventional low power...
This paper presents a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays is dramatically reduced...
This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At...
A successive approximation analog-to-digital converter (SA-ADC) for biomedical application is presented. It is based on 0.18-mum standard CMOS technology and operates at low supply voltage at 1 V. Boosted switch for sample-and-hold stage, split capacitor array for DAC, and clocked rail-to-rail comparator are used to achieve low-power consumption. The ADC has signal-to-noise-and-distortion ratio of...
A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for biomedical applications is presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator is used for low power consumption. It is realized in 0.18 mum standard CMOS technology. This ADC has signal...
This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18 um CMOS process, the 12-bits, 40 MS/sec ADC core consumes 7...
In this paper, a wideband LC VCO with small Kvco fluctuation for RFID synthesizer application is designed using SMIC 0.18 mum standard CMOS process. The switched capacitor array and switched varactor array are used for wideband design. The VCO exhibited Kvco fluctuation of only 29%, which is about one third that of a conventional VCO. The simulation results show that the tuning frequency range is...
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