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A wideband LC voltage-control oscillator (VCO) is designed based on SMIC 0.18μm CMOS process, which has wide tuning range by using the switched capacitor array, while the phase noise is reduced after using the differential inductance of high quality factor and the filter method. Simulated results show that the VCO has the tuning range of 23.3% from 2.12GHz to 2.68GHz, and the phase noise of -128.1dBc/Hz...
A 5th-order Chebyshev active RC complex filter for wireless sensor networks with automatic frequency tuning is presented in this paper. This filter is synthesized from 5th-order low-pass LC prototype, and designed using leapfrog structure. An automatic frequency tuning is used to prevent the deviation of the RC constant of the filter. This filter is fabricated in TSMC 0.18μm CMOS process. The measurement...
A biomedical electronics interface to detect heart signals is presented including a reconflgurable full differential fifth-order Bessel Gm-C filter and a 12 bit low-power fully differential successive approximation register analog-to-digital converter (SAR ADC). The total fully differential structure reduces the input signal noise and distortion effectively. A switch array is used in Gm-C filter to...
Based on TSMC 0.18μm 1P6M RF CMOS process, a 4th-order Butterworth analog low-pass filter (LPF) used in the transmitting link of 2.4GHz Wireless Sensor Network (WSN) radio frequency (RF) front-end is designed in this paper. In this design, active-gm-RC structure is derived, and it can achieve the same low consumption performance as the gm-C structure while have better linearity than that of the gm...
A successive approximation ADC based on the C2C DAC architecture is introduced. The ADC designed in a 0.18 ??m CMOS 2 Poly 4 Metal process uses a hybrid capacitive DAC combining the best of the binary weighted capacitive array and the C2C array. C2C ladder based architectures are very attractive for implementation because of its small area, high speed and low power consumption. However a major drawback...
Digitally controlled oscillator (DCO) for digital audio broadcasting (DAB) is proposed using 0.18 ??m CMOS process parameters with 1.8 V supply voltage. In this paper, the proposed DCO consist of tri-state inverter array and calibration block. Tri-state inverter array is 5-stage ring oscillator and each stage has 160 tri-state inverters. Calibration block is composed of 64 NMOS pass transistors and...
Today's communication systems require high-performance low-cost ADCs with emphasis on low power, and the ability to IF-sample to reduce receiver complexity. Further, the often-overlooked metric of small-signal linearity quantified by SFDR for less-than-full-scale inputs is important, especially in the presence of large interferers. This 16 b pipeline ADC achieves 78.7 dB SNR, 78.6 dB SNDR and 96 dB...
This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18 um CMOS process, the 12-bits, 40 MS/sec ADC core consumes 7...
In this paper, a wideband LC VCO with small Kvco fluctuation for RFID synthesizer application is designed using SMIC 0.18 mum standard CMOS process. The switched capacitor array and switched varactor array are used for wideband design. The VCO exhibited Kvco fluctuation of only 29%, which is about one third that of a conventional VCO. The simulation results show that the tuning frequency range is...
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