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Because of the high computation demand for multimedia applications like video decoding, there is a need to develop flexible and high performance reconfigurable computing architectures. Taking video decoding algorithm as an example, we propose a reconfigurable computing realization solution of multimedia application. Based on the analysis of parallelism in video decoding algorithm, a hardware platform...
Java is one of the most popular programming architectures because of its platform-independence. Its platform-independence depends on Java virtual machine JVM. Compared to executing class file on hardware JVM, executing class file on software JVM is much slower. By studying we master the component architecture and the working principle of software JVM based on the class file to explain the implementation...
Chip Multicore Processor (CMP) has become the mainstream microprocessor architecture in nowadays industry and academic literature. With the progress of CMP hardware developing and researching, software issues become more and more prominent. Coupled with these developments, many institutes and universities change their curriculums of computer architecture related courses. But the problem is do we really...
NVIDIA CUDA and ATI Stream are the two major general-purpose GPU (GPGPU) computing technologies. We implemented RankBoost, a web relevance ranking algorithm, on both NVIDIA CUDA and ATI Stream platforms to accelerate the algorithm and illustrate the differences between these two technologies. It shows that the performances of GPU programs are highly dependent on the utilization of GPU's hardware memory...
We design and implement a Mandatory Access Control (MAC) system in distributed virtual computing environment, named DVM-MAC, aiming to provide distributed trust through enforcing MAC policies. In DVM-MAC, Prioritized Chinese Wall (PCW) model is implemented to control potential covert channels between VMs in both single node and distributed environment. A policy enforcement module locates inside Xen...
A configurable fixed-point multiplier for digital signal processing (DSP) applications is proposed in this paper. It is implemented in four pipeline stages. The proposed multiplier supports multiple-precision operations, including one 32??32, two 16??32, two 16??16 or four 8??8 signed/unsigned multiplication operations and 16-bit or 8-bit dot product/double dot product operations. It is modeled in...
Field-programmable gate arrays (FPGA) are drawing increasing interest because of its performance, power consumption and configurability. They execute wide range of parallelizable algorithms which changes in accordance to variations in wireless channel statistics are utilized in smart antenna array embedded systems. In this article, we've described the FPGA implementation of a QRD processor that enables...
This paper presents an efficient and reconfigurable co-processor to calculate Mahalanobis distance, which is the most computation-intensive part in the GMM (Gaussian Mixture Models)-based classifier. The Mahalanobis distance's calculation is divided into three parts (vector-vector subtraction, matrix-vector multiplication, and vector-vector multiplication) and these three parts can operate in a parallel...
This design is for transplanting and using SQLlite database management system on μC/OS-II, the embedded real-time operating system. The design has used μC/OS-II, the open-source operating system, μC/FS, a file system transplanted on μC/OS-II, and the sqlite database. By studying their design principles and methods, clarifying the overall structure and the links between the various parts, I try to...
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