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The goal of this paper is to reduce the power and area of the Static Random Access Memory (SRAM) array while maintaining the competitive performance. Here the various configuration of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless four-transistor (4T) SRAM cell in deep submicron (130nm, 90nm and 65nm) CMOS technologies. Then it is simulated using HSPICE to check...
The adder circuit is used as a main component in the multiplier circuits. The Baugh-Wooley, Braun and CSA multipliers are designed by using our proposed adder cell. The proposed adder circuit is designed by using Shannon theorem. The multiplier circuits are schematised by using DSCH2 VLSI CAD tool and their layouts are generated by using Microwind 3 VLSI CAD tool. The proposed adder based multiplier...
The effective design of semiconductor memory pertaining to the power consumption, speed and area penalty has always been the crucial task in embedded computing applications. The work presented in this paper is exact and innovative mathematical model based implementation of 32 kb SRAM optimized for power and speed. The model has been developed for a cell, array, and pre-charge, I/Os and periphery devices...
Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multipliers and the 2D bypass multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% of the...
A 10-bit successive approximation analog-to-digital converter (ADC), with offset correction circuitry and a tunable series attenuation capacitor is presented for implantable biosensor applications. The ADC is designed in a standard 0.13 ??m CMOS process technology and can operate with supply voltages down to 0.6 V. The ADC uses MOSFETs that are designed to operate in the sub-threshold region of operation...
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