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This paper proposes a window-based image processing architecture that minimizes data activities. This architecture has a mapping structure between the line buffer and the window buffer. Each buffer handler writes or reads pixel data in one direction. This feature allows the designer to use a FIFO memory, as well as dual port random memory in the proposed architecture. Thus, the designer can select...
The goal of this paper is to reduce the power and area of the Static Random Access Memory (SRAM) array while maintaining the competitive performance. Here the various configuration of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless four-transistor (4T) SRAM cell in deep submicron (130nm, 90nm and 65nm) CMOS technologies. Then it is simulated using HSPICE to check...
This paper proposes a simple and practical RAID reconstruction optimization scheme, called JOurnal-guided Reconstruction (JOR). JOR exploits the fact that significant portions of data blocks in typical disk arrays are unused. JOR monitors the storage space utilization status at the block level to guide the reconstruction process so that only failed data on the used stripes is recovered to the spare...
A novel two-dimension (2-D) parity checking architecture is proposed for radiation-hardened by design (RHBD) SRAMs, which are insensitive to radiation-induced single-event upsets (SEU). The common 2-D parity checking method and its limitations in high density RHBD SRAMs are discussed. The novel architecture, which could be used to correct up to four adjacent upset errors, is more suitable for protecting...
The effective design of semiconductor memory pertaining to the power consumption, speed and area penalty has always been the crucial task in embedded computing applications. The work presented in this paper is exact and innovative mathematical model based implementation of 32 kb SRAM optimized for power and speed. The model has been developed for a cell, array, and pre-charge, I/Os and periphery devices...
We describe L1 cache designed for QUALCOMM??'s latest-generation digital signal processor (DSP) core. The cache is 32KB with variable associativity (4 to 16 ways) and is pseudo-dual-ported. Dual access is achieved by banking the cache in a way that minimizes bank conflict to less than 1%. The cache operates at 600 MHZ under worst-case PVT conditions and dissipates 100.8 pJoule per access at 1.2V....
Block memory or custom memory is one of the most important features in the Structured ASIC design. But block RAM is not suitable to form small memory array and also limited to the pre-defined location. On the other hand, the distributed memory is one of the most important features in FPGA to support small size memory application and available anywhere across the chip. But the distributed memory is...
Testing and diagnosis techniques play a key role in the advance of semiconductor memory technologies. The challenge of failure detection has attracted investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. March algorithms are widely used in SRAM testing to detect and diagnose SRAM fault model since they are relatively simple and yet providing...
This design is for transplanting and using SQLlite database management system on μC/OS-II, the embedded real-time operating system. The design has used μC/OS-II, the open-source operating system, μC/FS, a file system transplanted on μC/OS-II, and the sqlite database. By studying their design principles and methods, clarifying the overall structure and the links between the various parts, I try to...
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