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In this paper, the effects of package level structures and material properties on solder joint reliability subjected to impact loading are investigated by the integrated experimental testing, failure analysis, and finite element modeling. Three different package structures: ball on I/O wafer level package (WLP), copper post WLP, and chip-scale (CS) ball grid array (BGA) package, are studied. Experimental...
Hydrostatic stress of Cu damascene interconnects was calculated by using finite element method in the present work. The analytical work was performed to examine the distribution of hydrostatic stress and the effect of different line width in the Cu interconnects. Then a model of atomic diffusion was presented and used to calculate the size of stress-induced voiding according to result of hydrostatic...
Flip chip (fc) packaging has been practiced for many years but mainly for high end computer and certain automotive devices. RoHS has driven the conversion from lead-based fc bumps to lead-free (Pb-free) bumps. Pb-free was adopted more readily in consumer and mobile applications than in high reliability applications. A few years back, Intel introduced copper pillars (CuP) as an alternative to high...
A combined driving force model consisting of three driving forces is implemented for copper dual damascene line-via interconnects using finite element method. Good agreement is found between the experimental and computational results on the void volume at failure and time varying resistance change during electromigration stressing. The void evolution is also computed showing the process of the void...
In the last half a century, the complexity of electronic systems has undergone a sustainable rapid development stage following the Moore's law: the density of integrated circuits (ICs) was doubled every two years. As a result, electronic devices become more miniaturized in space and contain more power in unit volume. Electronic package has to deal with highly increased I/Os with fine soldering pitch...
This paper presents a systematic underfill selection and characterization methods for 21 ×21 mm2 Cu/low-K flip chip packages (65 nm technology) with 150 μm bump pitch. This paper has also correlated the underfill characterization methods with the reliability results of 15×15 mm2 and 21×21 mm2 Cu/low-K flip chip packages. From the validations of underfill selection and characterization approach with...
Through-Silicon Vias (TSVs) have recently aroused much interest because it is a key enabling technology for three-dimensional (3-D) integrated circuit stacking and silicon interposer technology. In this study, a 3-D 1/8th symmetrical nonlinear finite element model of a stack die TSV package was developed using ANSYS finite element simulation code. The model was used to optimize the package for robust...
The fabrication of embedded passives represents a promising solution for system in package (SiP) regarding the reduction of size and assembly costs. But the thermo-mechanical deformation caused by residual stress generated from embedded passives processing have a significant impact on reliability of embedded passives. Due to the complication of embedded passives processing, there are several challenges...
Deformation Measurements under thermo-mechanical load are quick and useful tool to increase the reliability of electronic products and to verify Finite Element Models (FEM). Two Examples demonstrate the advanced use.
In this paper, the investigation focuses on the copper stud bump solder joint thermal-mechanical reliability. The copper stud bump processing is simulated by FEM software Ansys/Ls-dyna, and then the relationship between the copper stud bump and processing parameters (bonding force, ultrasonic power, bonding time and bonding temperature) is studied. Based on the simulation result, the dimension of...
Hydrostatic stress of Cu damascene interconnects were calculated by using commercial finite element software in the present work. The analytical work was performed to examine the distribution of hydrostatic stress and the effect of different low-k dielectrics and barrier materials in the Cu interconnects. The results indicate that the hydrostatic stress is strongly dependent upon different low-k dielectrics...
System-in-a-Package (SiP) aims to integrate a functional sub-system with one or more semiconductor chips along with passive components onto a substrate. SiP is transferred molded to the OEM for second level assembly using industry standards and high volume equipment. In most recent applications (high I/O density, improved electrical performance), LGA (Land Grid Array) is a very practical solution...
A new bonding process has been developed for producing direct bonded aluminum (DBA) substrates using aluminum nitride (AlN). A transient eutectic liquid phase forms in aluminum-X (X = silicon, germanium, silver, or copper) systems at the interface between the aluminum foil and the AlN substrate. The aluminum-X liquid phase transiently contacts the AlN substrate prior to isothermal solidification by...
This study serves to validate the predictive finite element modeling approach for the solder joint thermal fatigue life analysis, with emphasis on the applicability to various lead-free solder joints. The three packages involved in the study are 8??8 mm PBGA, l0??l0 mm QFN, and 51??51 mm CBGA. They are designed to consist of SAC387, SAC305, ??SAC305 ball + SAC387 paste?? and ??SAC387 ball + SAC305...
This paper presents mining the worst thermal fatigue life of solder joints on chip components used in vehicle electronics. The authors proposed an isothermal fatigue test method using real size solder joints to get the fatigue properties. The Manson-Coffin's law given by this method could improve the agreement between the simulation model and experimental results. Based upon the Manson-Coffin's law...
In this paper, thermo-mechanical reliability of a variety of state-of-art wafer level packaging (WLP) technologies is studied from a structural design point of view. Various WLP technologies, such as Ball on I/O with and without redistribution layer (RDL), Ball on Polymer with and without under bump metallurgy (UBM) process, and encapsulated Copper Post WLPs, are investigated for their structural...
In the through silicon via (TSV) structure for 3-dimentional integration (3DI), large thermal-mechanical stress acts in the BEOL layer caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials. The resulting high-stress region is thought to be the critical point for the initiation of the cracking or the de-lamination that affects the mechanical reliability. In this study,...
Portable products as well as some larger products may see failures by a high strain rate mechanical loading like that seen in a high or low level drop/shock event. Within the portable product industry there is a wide range of product design, usage and loading conditions. Because of this, standards such as JEDEC, which is meant to generate comparative results addressing component reliability, do little...
The interface of epoxy molding compound (EMC) and Cu is known to be one of the weakest points in the electronic package design. Self-assembly monolayer (SAM) has been suggested as adhesion promoter of EMC-Cu system. Due to the length scale issues, traditional finite element or Molecular dynamic simulation can not individually simulate the behavior of the EMC-SAM-Cu interface in electronic packages...
The temperature dependent driving force for stress induced voiding of Cu dual damascene interconnects has been studied using finite element modeling. Both 2D axisymmetric and 3D models have been investigated. Interconnect test structures have been simulated at temperatures ranging from 25 to 300degC and a stress free temperature for the structure is demonstrated, consistent with analytical modeling...
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