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In this paper, a comprehensive modeling is carried out to investigate the dynamic behaviors of WL-CSP subjected to both flat and vertical drop impacts. The non-linear dynamic properties include solder, Cu pad and the metal stacking under the UBM. Both of the JEDEC standard flat drop test and the vertical drop test modeling for different solder bump height are studied. The results showed that, in the...
Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional stacking of thin dies is demonstrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm × 10 mm × 0.4 mm and solder ball pitch of 0.4 mm. As part of the development several key processes...
Embedded Wafer Level Package (eWLP) is designed and developed. The eWLP consists of one silicon die encapsulated with a mold compound and its size is 12mm × 12mm × 0.2mm. The assembly process of eWLP consists of reconfiguration of the dies on an adhesive tape, followed by molding, thinning and rerouting distribution layer (RDL) process. Finite Element Modeling (FEM) is used to understand the stress...
We present the results of study on the manufacturability and reliability of ALX211 polymer in wafer level packaging processes and structures. Previously, the processing windows of ALX211 polymer and the impact of the delays between processing steps on the stability of the process were studied. In this paper, we present a new method to achieve high resolution using ALX211, by putting a certain period...
This paper presents the effect of the reflow oven type to the intermetallic (IMC) formation and solders joint reliability for the wafer level packages (WLPs). Two common used reflow oven in electronic manufacturing industry which are conduction and convection oven have been studied. Four reflow profiles with same peak temperature and wetting time for both ovens were developed. In this study, two low...
2nd level reliability performance during drop impact is critical for Wafer Level Packages (WLP). Accompanying the popularization of portable and mobile phone products, high reliability under board level drop test is a great concern to semiconductor manufacturers. A 0.4mm pitch Cu under bump metallization (UBM) type has been developed for mobile computing application. In this paper presents the impact...
For the demands of multifunction, high density interconnection, high performance and integration of homogeneous or heterogeneous ICs, three dimensional IC (3DIC) packaging technologies by through silicon via (TSV) and microbump were widely studied recently. Intending to learn the reliability performance of Pb-free microjoints, 4 chips were interconnected with one Si interposer by Sn2.5Ag microbumps,...
As high-speed, high-density, and high-performance are the primary IC development targets, packaging technologies play a key role to bring out the best performance of those ICs. In this paper, an active component formed by an active chip embedded technology is developed for the package of a high speed DDR2 memory device. Embedding of semiconductor chips into an organic substrate provide a solution...
A good solution to meet the need of miniaturization and low cost for micro-electronics packaging is wafer level package technology. But thermal mechanical reliability problem which generated from the coefficient of thermal expansion (CTE) mismatch between the chip and the PCB limit the application of larger size wafer level package. To solve this problem, the prototype of compliant package is proposed...
In this paper, the state-of-the-art results of research and development in wafer-level packaging (WLP) is reviewed. The paper starts from the introduction of several fan-in wafer-level packaging technologies. The focus is given on the fan-in WLP reliability performance as related to the structural differences. New failure mechanisms that appear in build-up stack layers are discussed. Next, emerging...
The increasing demand for portable electronics has led to the shrinking in size of electronic components and solder joint dimensions. The industry also made a transition towards the adoption of lead-free solder alloys, commonly based around the Sn-Ag-Cu alloys. As knowledge of the processes and operational reliability of these lead-free solder joints (used especially in advanced packages) is limited,...
In this paper, we have developed the evaluation results of low cure temperature (less than 200 deg C) dielectric materials in terms of process ability and adhesion on SiN and mold compound substrates. The results showed that the low cure temperature dielectric materials have good adhesion on SiN and mold compound substrate. Integration of thin film passives like inductors, capacitors and band pass...
3-D technologies open a wide range of chip integration possibilities for microelectronic systems. Most of these technologies are using through-silicon vias (TSV). One disadvantage of this technology is the high investment for new equipment and processing cost for Si etching and metallization. The thin chip integration technology (TCI) presented in this paper is based upon existing WLP infrastrcuture:...
Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. In this paper, a new compliant Wafer Level Package technology is proposed which can accommodate the CTE mismatch between the chip and PCB substrate and consequently should be more reliable without the application of underfill. The purpose of this study is to...
In this paper, thermo-mechanical reliability of a variety of state-of-art wafer level packaging (WLP) technologies is studied from a structural design point of view. Various WLP technologies, such as Ball on I/O with and without redistribution layer (RDL), Ball on Polymer with and without under bump metallurgy (UBM) process, and encapsulated Copper Post WLPs, are investigated for their structural...
In this study, three examples of failure analyses of electronic packaging by using the finite element method are presented. These are: (1) the failures (delaminations) near the interface between the filled copper and the silicon and between the copper and the silicon dioxide dielectric of the TSV of a 3D system-in-package (SiP) due to the local thermal expansion mismatch between the silicon and the...
In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the UIW (Uniformity in Wafer) could be sharply decreased from 6.37% after plating to 1.7% after polishing and even to 1.7% after reflow throughout the entire 4 inch wafer.
With the demands of miniaturized solutions that are able to handle increased heat dissipation, the use of silicon substrates with through-silicon vias (TSV) in electronics modules becomes more and more interesting. Shorter signal path, better cooling of tracks, better impedance control and smaller foot-prints are some of the advantages. This also avoids some RC delays of long, in-plane interconnects...
In this study, wafer level NCA patterning processes for CIS modules have been demonstrated and the effects of whole processes on NCAs were also investigated. At first, NCA solution was directly coated on a bumped wafer with Cu passivation on an image sensing area. Cu was sputtered on a NCA coated wafer, and then sputtered Cu layer was patterned using a photoresist lithography method. Subsequent NCA...
PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch...
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