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As the security is becoming more and more important these days, we still should not forget about reliability. When designing a cryptographic device for some mission-critical or another reliability demanding system, we need to make the device not only attack-resistant, but also fault-tolerant. There are many common fault-tolerant digital design techniques, however, it is questionable, how these techniques...
The reliability of FPGA based hardware designs has become an important field of research particularly for space computing. Traditionally, redundancy is utilized in FPGA based designs to achieve reliable or error-tolerant computing. However, the redundant designs vary according to the granularity level and the voter placement algorithms used for the hardware design. The resulting circuit configurations...
In order to improve the reliability of SpaceWire Bus, this paper makes a study of SpaceWire redundancy. In a spacecraft where SpaceWire is used, Redundancy is an important fault-tolerant technology to improve the reliability of the system. However, the regulation of redundancy does not be involved in the current standard of SpaceWire, so, it is necessary to study redundancy technology of SpaceWire...
Today system reliability, availability, serviceability, and manageability (RASM) are becoming more crucial as computer based systems continue to increase in complexity and importance to our daily lives. Redundancy is a viable approach to improve the RASM attributes of a system. There are many forms of fault tolerant/redundant system architectures employed in both commercial and military /aerospace...
Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of...
According to the shrinking feature size of the VLSI circuits it is expected that nano scale devices and interconnections will introduce unprecedented level of defects and architectural designs need to settle with the uncertainty result at such scales. Several approaches for implementing the fault tolerance systems are already investigated. Most of these methods are applicable also in the case of high...
Field Programmable Gate Arrays (FPGAs) are becoming an appealing solution in space applications due to their high performance, low cost and flexibility. Unfortunately, reconfigurable SRAM-based FPGAs are extremely susceptible to radiation induced Single Event Upsets (SEUs), especially when COTS components are largely adopted today. SEUs can not be eliminated completely using processing or layout solution,...
This paper presents a digital control architecture that demonstrates operating standby redundancy for a voltage source inverter (VSI) controller. The reliability analysis shows the increased lifetime of the VSI using a standby redundant controller. The VSI control system is designed to switch from the primary to the secondary controller when a fault to the primary controller occurs. Simulated and...
This paper presents a novel bio-inspired artificial system that is based on biological prokaryotic organisms and their artificial model, and proposes a new type of fault tolerant, self-healing architecture. The system comprises of a sea of bio-inspired cells, arranged in a rectangular array with a topology that is similar to that employed by FPGAs. A key feature of the array is its high level of fault...
As technology shrinks, critical industrial applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as single event effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means...
This paper describes an efficient approach of applying mitigation to an FPGA design to protect against single event upsets (SEUs). This approach applies mitigation selectively to FPGA circuit structures depending on their importance within the design. Higher priority is given to structures causing "persistent" errors within the design. For certain applications, applying selective mitigation...
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