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This paper presents a scalable MIM capacitor model that is applicable at RF and mm-wave frequencies. The model parameters are obtained from electromagnetic simulations and verified by measurements over a wide range of geometry parameters. A de-embedding method is described that is based on two through structures.
This paper presents a novel technique of performing correlation-considered statistical interconnect parasitic parameter extraction on 40-nm process technology. Five test structures are designed for the extraction. Then, 3-D simulations are performed, and typical interconnect technology profile (ITP) file is extracted. Based on the full mapping measurements of test structures, their distribution analysis,...
The paper describes a methodology for development of LVS and LPE rule sets adapted for microelectromechanical technologies. The method is applied on an existing multipurpose MEMS process. To evaluate the accuracy and performance of the proposed method, parasitic extraction is performed on several different devices designed with the chosen MEMS technology. The LPE results are compared to reference...
Multi-finger transistor layout is widely used in CMOS circuit designs. Comparing with single-finger transistor layout, its main features include effectiveness in reducing circuit physical size and improving device matching. However in CMOS ring oscillator design, considerable performance discrepancies are found between multi-finger transistor layout and single finger transistor layout. Despite such...
In this paper, we present a layout driven approach used to fill empty space within MCM, with 3D high density decoupling capacitors. In a first time, a description of the innovative 3D unit cell is done based on process considerations. Then the method including the whole design flow is described and validated with the help of specific test cases and RF characterization data up to 6 GHz. A physical...
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