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This paper describes and demonstrates the viciLogic platform as an effective pedagogical solution for online technology enhanced learning, assessment and prototyping of digital logic and computer architecture systems. viciLogic provides an opportunity to improve digital systems education globally and to develop the global digital logic design community, with a positive impact on future digital logic...
The Embedded system is controlled with the combination of hardware and software. They are usually processed by a microprocessor / microcontroller that execute instructions which are present in ROM. The term "embedded" reflects to the fact that they are part of the system. Real-Time Operating System (RTOS) combines with two thoughts "real-time" and "operating system"....
In this paper, an effective reduction method of the number of subproblems for the design of CSD (Canonic Signed Digit) coefficient FIR (Finite Impulse Response) filters using BB (Branch and Bound method) is studied. The problem can be formulated as a mixed integer programming problem. The problem can be optimally solved by using the BB. For solving the problem, it is required to solve a large number...
Current studies about decoding Fast protocol in the FPGA platform are always implemented using serial communication technique and for some certain Fast Templates. This paper presents the FPGA hardware design of accelerating the decoding process in parallel and cutting down the cost of changing Fast Templates with flexible decoders. The complete system has been simulated and tested in SystemC Platform.
In this paper, we propose a Performance Enhancement Guaranteed Cache (PEG-C) to ensure performance benefit in the worst case while achieving as good average-case performance as a regular hardware-controlled cache. Our experiments indicate that with a small number of preloaded data and a simple hardware extension, the PEG-C can guarantee performance enhancement in the worst case while achieving the...
Cache compression seeks the benefits of a larger cache with the area and power of a smaller cache. Ideally, a compressed cache increases effective capacity by tightly compacting compressed blocks, has low tag and metadata overheads, and allows fast lookups. Previous compressed cache designs, however, fail to achieve all these goals. In this paper, we propose the Skewed Compressed Cache (SCC), a new...
A novel eye detection method based on template matching is proposed for glasses-free 3D device. Before matching, get the average eye template through a great quantity of eye images, splice several average templates into a chessboard template. Then locate the position of eyes by calculating the correlation coefficient between template and the candidate image. It has been testified that these algorithm...
Heterogeneous multi-core FPGAs contain different types of cores, which can improve efficiency when used with an effective online task scheduler. However, it is not easy to find the right cores for tasks when there are multiple objectives or dozens of cores. Inappropriate scheduling may cause hot spots which decrease the reliability of the chip. Given that, our research builds a simulating platform...
The future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, realtime and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly...
This paper deals with the Embedded platform for didactical aids development. It shortly summaries one of the aids that was derived from the base embedded platform. The design of the aid was focused on special pedagogues needs in field of specific learning disabilities (SLD). It will aim to reduce the SLD like dyscalculia, conceptual thinking, motor activity etc. This aid was build and its contribution...
The paper was proposed to design an electronic system, in order to provide a solution to irregular waste disposal system. The designed system makes use of biosensor sensor, weight sensor and height sensor to detect overflow of the waste in the dust bin and the extent of pollution caused by unwanted toxic gases from the bin. These sensors are further fed to the controller which would help the GSM module...
Packet filter system based on high speed match engine of REGular EXPressions (REGEXP) plays an important role in domain of Intrusion Detection System (IDS), Deep Packet Inspection (DPI) system, network security and traffic monitoring, etc. However, the existing filter schemas suffer from several deficiencies in matching speed and memory footprint, such as traditional DFA matching, single-level signature...
High-dimensional torus networks are becoming common in flagship HPC systems, with five of the top ten systems in June 2014 having networks with more than three dimensions. Although such networks combine performance with scalability at reasonable cost, the challenge of how to achieve optimal performance remains. Tools are needed to help understand how well the traffic is distributed among the many...
As is known, masking and hiding are two quite effective ways to perform protection against the side channel attacks. However, since recent years the effectiveness of side channel attack has been highly improved, the traditional way of masking has been invalidated, especially when it comes to High-Order DPA attacks, which presents a real practical threat according to the recent results. In this article,...
This paper is dedicated to the presentation of the Tempus project “rESeau maghrébIn de laboratoirEs à distance”, eSience, which aims to create an eLab for the realization of remote practical courses in Maghreb countries (Algeria, Morocco, Tunisia). In this paper, we present a prototype for a remote laboratory for electronics implemented in the National Electronics and Telecommunications school of...
The MEMOCODE design contest for 2014 was centered around the emulation of the 1978 Taito video game Space Invaders. The challenge is to improve the speed of a cycle-accurate software emulator for the game. Contestants had a month toope improve the provided code, which already ran fairly well on the ARM-based Raspberry Pi platform. Entries were judged on how much faster their code ran and its quality...
Testbeds are a stage between the simulation and the production stages. To this end they must be as close as possible to production environments (i.e. real hardware, on the field deployments) while also keeping the traits of experimentation facilities (i.e. fault tolerance, ease of deployment, testing and data collection). This paper presents WiBed, a FOSS platform for WiFi testbeds based on OpenWRT...
Bit-precise reasoning (BPR) precisely captures the semantics of systems down to each individual bit and thus is essential to many verification and synthesis tasks for both hardware and software systems. As an instance of Satisfiabiliy Modulo Theories (SMT), BPR is in essence about word-level decision procedures for the theory of bit-vectors. In practice, quantiers and other theory extensions, such...
Recently, Hadoop attracts much attention of engineers and researchers as an emerging and effective framework for Big Data. HDFS (Hadoop Distributed File System) can manage huge amount of data with high performance and reliability using only commodity hardware. However, HDFS requires a single master node, called a NameNode, to manage the entire namespace of the file system. This causes the SPOF (Single...
Via the survey based on 400 eleventh grade students from five distinct high schools in Shanghai, we learned about the actual situation of CSCL and its connection with high-school level courses in Shanghai. Through this research, we found that the electronic equipment is not a restricted factor for CSCL in high schools of Shanghai any more. On the other hand, it is shown that the teachers were not...
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