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This article proposes a modification of the standard Linux scheduler for a support of a reconfigurable heterogeneous multiprocessor system. The standard Linux scheduler is limited to a homogeneous multiprocessor system only. The addition of the processing core with a different feature requires modification of a decision algorithm of the scheduler as a heterogeneous task cannot be executed on any processing...
While addressing cache coherency in shared memory multiprocessors, traditional snoopy based pure write update (PWU) and pure write invalidate (PWI) protocols have many issues including low bandwidth, high memory latency, and large cache miss ratio. This paper presents a directory based hybrid cache coherence protocol to better address the cache coherency and improve performance of shared memory multiprocessors...
As multiprocessor systems are continuing to be adopted in academic laboratories and industry, researchers and application developers are routinely designing multiprocessor systems from the low level. Before they can validate their ideas, most of their time is spent on handling massive engineering details. It includes building a multiprocessor system from scratch by handling details of IP components...
A multiprocessor which shares the memory among processors and uses multiples translation lookaside buffers (TLBs) can face various problems. One such problem is the problem of inconsistency which may occur when the page table entry (PTE) is updated because of the multiple copies of same page table entry in various TLBs. Commonly, the inconsistency problem exists in virtually tagged caches, which keep...
Modern high-performance embedded systems are characterized by heterogeneity of the employed processing elements: general-purpose processors working together with embedded processors and with dedicated hardware accelerators or high-speed I/O interfaces. Communication among these processors and interfaces is one of the crucial aspects of the development of such systems. In this paper we present a communication...
Multi-Processor Systems-on-a-chip (MPSoCs) are currently the most common implementation technique to build complex systems that provide high performance according to both timing and power restrictions for electronic systems. Both many-core (usually homogeneous multiprocessing) and multi-core (more often heterogeneous) require providing some complex parallel programming methods together with architectural...
The article presents multiprocessor system on chip (MPSoC), which uses dynamic partial reconfiguration of FPGA (Field Programmable Gate Array) to change parts of system depending on performed task requirements. The multiprocessor system is based on softcore processors running modified GNU/Linux operating system. The individual parts are designed for connection via standard interface for high performance...
Verifying the execution of a test program against the memory consistency model is known to be NP-hard. Because of lacking extra observability, verifying the memory consistency model in post-silicon stage is even harder than in pre-silicon stage. In this paper, by identifying the pending windows of microprocessor and introducing the resultant time order restrictions, we propose a low time complexity...
In this paper an integer linear programming (ILP) model is proposed for identifying the optimal resources allocation and application partitioning on FPGA-based hybrid MPSoC, including the memory allocation for each processing unit and total BRAM usage on the device. The motivation behind this work is the reduction of the necessary exploration time for the identification of the optimal hybrid MPSoC...
The Method of Moments (MoM) technique is the backbone of all computational methods for the modeling and simulation of complex systems. With applications including fluid mechanics, electromagnetics, and fracture modeling, MoM is versatile and has laid the foundation for modern optimization methods. Modeling and simulation is absolutely necessary for the success of all complex engineering problems of...
In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core...
The hardware design of Godson-3A processor adopts the scalable distributed multi-core structure which is based on a 2D mesh. It can make use of multi-chip interconnection to construct a unified topology structure for board level or system level. This kind of interconnected system can't achieve entirely by hardware design, and it also needs the reasonable design of the BIOS and upper software. As the...
This paper investigates the modeling of hardware interface modules in cycle accurate simulators. The implemented modules are integrated into a C++ multi-processor system-on-chip (MPSoC) simulator. The implementation of hardware interface models is driven by the following desired features: easy integration into the simulation model of the MPSoC and easy configuration. Regarding the first feature, it...
Analytical processor performance modeling has received increased interest over the past few years. There are basically two approaches to constructing an analytical model: mechanistic modeling and empirical modeling. Mechanistic modeling builds up an analytical model starting from a basic understanding of the underlying system - white-box approach - whereas empirical modeling constructs an analytical...
Future general purpose architectures will scale to hundreds of cores. In order to accommodate both latency-oriented and throughput-oriented workloads, the system is likely to present a heterogeneous mix of cores. In particular, sequential code can achieve peak performance with an out-of-order core while parallel code achieves peak throughput over a set of simple, in-order (10) or single-instruction,...
Recognizing the strategic importance of embedded computing for industry and society, the European Commission formed, together with industry, academia, and national governments, the European technology platform ARTEMIS (Advanced Research and Technology for Embedded Intelligence and Systems) in 2004. It is one goal of ARTEMIS to develop a cross-domain embedded system architecture, supported by design...
Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
The ongoing move of hardware platforms to many-core processor challenges the traditional software design methodology. It is critical to develop new programming paradigms and efficient ways to port legacy applications. This paper analyzed a typical packet processing application and also the cache hierarchy and behavior of Raw architecture many-core processor. It presented an easy to implement run-time...
In multicore processors, the execution environment is defined as the environment in which tasks run and it is determined by the hardware resources they get and the workload with which they are executed. Thus, different execution environments lead to different inter-task interferences accessing shared hardware resources due to conflicts with the other corunning tasks, making the WCET estimation of...
Multi-core system and the associated software parallelization techniques have become one of the major trends of SoC design. A multi-core system with high hardware efficiency and software parallelism has the potential of achieving higher system performance and lower power consumption. This paper reveals how system performance prediction and analysis for multi-core system can be done at early design...
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