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Content-addressable memory (CAM) is the hardware based particular type of memory device utilized for low power and high-speed application. CAMs are developed for precise application without sacrificing their search speed, and it is much faster than random accessmemory (RAM) in search application. CAM executes two essential functions storing and comparing. The additional circuitry during comparison...
Ethernet based secure VPLS (Virtual Private LAN Services) networks require to establish full mesh of VPLS tunnels between the customer sites. However, the tunnel establishment between geographically distant customer sites introduces a significantly high delay to the user traffic transportation.In this article, we propose a novel fast transmission mechanism for secure VPLS architectures to reduce the...
This paper is focused on the 5G-Crosshaul Packet Forwarding Element (XPFE), which is the packet forwarding element of the 5G-Crosshaul network architecture. The XPFE integrates multiple technologies which allow to transport traffic from multiple tenants and of different nature over the same infrastructure. Hence, the paper is focused on the performance of this essential element of our network, providing...
This paper presents the concept, traits, principle and structure of 64-bit high speed VLIW microprocessor. The microprocessor facilitates 16 kinds of operational function. Out of these, our main focus is on the add operation. The add operation is implemented using 64-bit adders namely, Carry Look-ahead Adder, Carry Select Adder, Ripple Carry Adder, Weinberger Adder, Ling Adder and Modified CSLA using...
Vedic maths based multiplier is a novel and high speed multiplier. Adder is one of the main components used in this technique. Using fast adder will enhance the overall performance of the Vedic multiplier. In this work, comparative analysis is done using different adder architectures in Synopsis Design Compiler with different standard cell libraries at 32/28 nm. Various Adder topologies like Ripple...
In this paper we discuss about 3 general issues on mesh topology in “networks on chip” (NOC): Utilizing multi-level mesh for delay reduction, using route by considering the mesh topology concept, and finally an optimal model of mesh topology named “multi-level mesh topology” which is defined based on 5-layer network model is suggested. In multi-level mesh topology we can see that this architecture...
Ultra-Dense Network (UDN) is a promising technology to cope with explosively increasing traffic demands. Delay is an important performance indicator in UDN. In this paper, we analyze the impacts of average sleeping time of BS and association radius on the mean delay in UDN. The explicit relationship between delay and the average sleeping time and association radius is presented. An M/G/1/N processor...
This work presents a study concerning the impact of Cloud Radio Access Network and virtualisation techniques in an operator's network, namely in terms of the necessary number of storage and processing nodes, and the links in between, taking increasingly network constraints into account (e.g., latency) as well as deployment ones (e.g., service area, deployment strategy, and expected proliferation of...
Software-defined networking (SDN) are the rising technology in near future to build programmable networks as a way to simplify the evolution of networks. It is a new networking paradigm with the main aim is to decouple forwarding hardware from control decisions. Several SDN architectures have been recently proposed and evaluated. Performance evaluation of these architectures, to study their scalability,...
Wireless Sensor Networks (WSN) plays a vital role in the modern communication mechanism. These are more vulnerable to attacks due to their basic limitations such as communication distance, memory, processing, throughput and power. In this paper we analyze communication delay and energy consumption of a WSN. We propose a Novel Dynamic Reconfigurable Network Monitoring Node (DRNMN), which controls the...
To mitigate the total power consumption in any circuit, ASICs or FPGAs, various conventional power gating techniques has been adopted depending upon the need of the application, dynamically controlled power gating procedure is one such power gating technique which can be used to reduce the total leakage power consumption of the circuit during the runtime. It can be applied on the real time application...
In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace...
Quantum cellular automaton (QCA) is an efficient and emerging nanotechnology to create quantum computing devices. It is polarization based digital logic architecture. QCA cell is the basic unit to build logic gates and devices in quantum domain. This paper proposes an effective design of logic gates and arithmetic circuit using QCA. Here the gates and circuits are designed using minimum number of...
Static Random Access Memory (SRAM) plays a most substantial role in the microprocessor world, but as the technology is scaling down in nanometers, leakage parameters and delay are the most common problems for SRAM cell which is basically designed for very low power application. Transmission gate is used to further reduced leakage current penetrating in the 8T SRAM cell. Comparative analysis is performed...
Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic...
Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic...
In this paper we study the influence of Weighted Round Robin (WRR) scheduling algorithm frame size to the performance of Crosspoint Queued (CQ) crossbar switch. In order to show that throughput and cell delay can be adjusted with appropriate WRR frame size, we analyzed switch for different values of frame size and under the unbalanced bursty traffic. We show that WRR scheduling algorithm achieve throughput...
Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
This paper describes a new required course in the Georgia Tech computer engineering curriculum, ECE 3030, Physical Foundations of Computer Systems. Traditional introductory courses take a constructive approach to logic design and computer organization. 3030, in contrast, introduces the major physical concepts underlying computation. It shows how they determine basic properties of computers such as...
In this paper, two novel energy efficient resource allocation schemes are proposed for beyond next generation mobile networks. The schemes take into account the clustering capability of base stations before assigning users to the base stations. A topology management scheme that adjusts the number of active base stations in accordance with the traffic load and also responds to QoS deterioration is...
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