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We present a digital system for measurement of neutron spectra in mixed gamma-neutron fields. The signal from a standard scintillation detector is sampled at rate up to 1 GHz, using 12-bit analog-to-digital converters. First stage of the signal processing is performed on a Virtex 6 FPGA and partial results are streamed through a fast Ethernet link to a computer, where the final processing takes place...
Networks-on-chip (NoCs) have become a new chip design paradigm as the size of transistors continues to shrink. Globally-asynchronous locally-synchronous (GALS) on-chip networks are proposed for solving issues such as large clock tree distribution and signal delay variations. More interestingly, for the GALS networks using m-of-n delay-insensitive interconnect, the asynchronous interconnect not only...
In this paper, we present the first multilevel implementation of the Harris-Stephens corner detector and the ORB feature extractor running on FPGA hardware, for computer vision and robotics applications. ORB is a fundamental component of many robotics applications, and requires significant computation. The design has been validated both in behavioural simulation and in implementation on an Arria V...
A solid state 3D scanner based on a pulsed laser diode source and narrow time gating of a 2D CMOS single photon avalanche diode (SPAD) detector array is presented. The imager uses an on-chip delay-locked loop to program the time gating of 40 sub-arrays individually. The prototype detector has 80 × 25 pixels with a fill factor of 32 % in the sensor area. The chip has been fabricated in a 0.35 μm high-voltage...
Directional dark matter detection seeks to reconstruct the angular distribution of dark matter particles traveling through the laboratory. A directional detector with high spatial resolution has the potential to increase the sensitivity per unit volume by over two orders of magnitude, but requires the development of a high-channel-count, high-speed readout system. This paper describes an FPGA-based...
Efficient detection and reliable matching of image features constitute a fundamental task in computer vision. When real-time operation is required, the solution to this problem becomes a real challenge, because of increased processing requirements. Scale Invariant Feature Transform (SIFT) is considered as a stable and robust algorithm for the extraction of invariant features, however special hardware...
This work presents the development and implementation of an ionizing radiation detector based on a commercial off the shelf CMOS image sensor and a FPGA. The response of the system was tested in irradiations with gamma photons, beta and alpha particles using different configurations of the image sensor. Finally, we analyze the possible uses of such configurations in the discrimination of events produced...
A 1 Volt, 8-bit, Successive Approximation Register Type ADC, with variable conversion time is implemented using FPGA SPARTAN-6 Board. The proposed ADC is design to achieve different number of conversion cycle for different sample values. Input signal as triangular wave with both positive and negative cycle is taken, But the DAC used in feedback is design to give analog output only for positive cycle...
This paper proposes a detailed evaluation of the impact of digital filters when applied to the Neutrinos Angra Experiment. The signals coming out from its front-end electronics are digitized and then sent to an FPGA where further processing might be carried out. In this context, this work proposes a set of peak amplitude estimators optimized to have minimum variance. Constrained optimization technique...
This paper describe the implementation of a lock-in amplifier (LIA) which conforms to the AXI standard for on-chip communication. The design and implementation is based on the Zynq field programmable gate array (FPGA) present in the open-source instrument RedPitaya. The designed architecture is a mixed solution between VHDL hardware modules and software modules, running within an ARM CPU. General...
The advancement and use of silicon photo multiplier (SiPM) technology has enabled portable devices for applications such as scintillation detection to be developed. The proposed analogue to digital converter (ADC) architecture and field programmable gate array (FPGA) system configuration advances on analogue signal processing methods, traditionally employed for gamma isotope identification applications...
As we have seen in this paper, FPGAs are a good candidate for implementing compute-intensive algorithms. Although the processing frequency is more than 10 times lower, their capability to process multiple data channels in parallel compensates for it and gives them an advantage in relation to CPUs. By comparing the results we see that the processing time was sped up by factor of 3 with 60% of the resources...
We present a portable 64-channel photon-counting system employing a monolithic array of Single-Photon Avalanche Diodes (SPADs) and a custom-designed Time-to-Digital Converter (TDC), for single-photon counting and timing applications. The system provides state-of-art singlephoton detection performance and time-resolved measurement capability, with timing precision down to 100 ps FWHM and linearity...
This paper presents the proposal of a new front-end readout electronics (RO) architecture for the ALICE Charged-particle Veto detector (CPV) located in PHOton Spectrometer (PHOS), and for the High Momentum particle IDentification detector (HMPID). With the upgrades in hardware typology and proposed new readout scheme in FPGA design, the RO system shall achieve at least five times the speed of the...
TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode front-end ASIC developed to readout the new inner tracking detector of the BESIII experiment, carried out at BEPCII in Beijing. The detector is planned to be installed during the 2018 upgrade and features an innovative three-layer triple-CGEM (Cylindrical Gas Electron Multiplier) with analog readout. The ASIC comprises 64 channels,...
This paper presents different miniature wireless brain computer interfaces (BCI) enabling synchronized optogenetics and electrophysiology recording for various experimental conditions. These devices, which are entirely built using commercial off-the-shelf components, are validated in-vivo with small transgenic mice. First, a system including 32 electrophysiological recording channels and up to 32...
We have defined a hyperspectral imager based on micro-mirror MEMS array, that features easily adaptable spectral resolution, adjustable acquisition time, and high spatial resolution independent of spectral resolution. We present the development of an integrated research prototype of the imager, that allows the control of both the micro-mirrors array and CMOS data reading from the same FPGA board,...
The upgrades of the Compact Muon Solenoid particle physics experiment at CERN's Large Hadron Collider provide a major challenge for the real-time collision data selection. This paper presents a novel approach to pattern recognition and charged particle trajectory reconstruction using an all-FPGA solution. The challenges include a large input data rate of about 20 to 40~Tbps, processing a new batch...
The seismograph is a kind of seismic prospecting instrument, detection zone is nearly hundreds of meters. Along with the digital technology application in the engineering seismograph, need to collect and transfer a large of data, and efficient data transmission is directly related to exploration efficiency. Therefore, this paper proposes a parallel data concentrator based on the technology of FPGA,...
Fault injection attack against embedded devices has attracted much attention in recent years. As a highly efficient fault injection, EM fault injection (EMFI) outperforms other injection means owing to its outstanding penetration capability in incurring local faults into security ICs. In this paper, we present an all digital countermeasure for detecting the on-the-fly EMFI attempts in silicon chips...
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