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As a step toward sustainable wireless sensing, we present a proof of concept system that uses a Plant Microbial Fuel Cells (PMFC) as a power source. To match the very low power production capabilities of the PMFC, we couple it with an ultra-low power wake-up receiver used as a trigger for sampling and transmission of the sensed value. We demonstrate that this combination, with a new, receiver initiated...
A low-voltage, ultra-low power sensor interface for electromyogram (EMG) signal acquisition is presented. The sensor interface consists of an amplifier and a SAR ADC that work from a 0.3V supply. The low-voltage amplifier topology provides a noise level of 26μVrms, 40dB gain and a state-of the art power efficiency factor (PEF) of 2.2 from a 20–425Hz bandwidth. Low-voltage supply improves the power...
An ultra-low power autonomous MPPT algorithm that maximizes the efficiency of a monolithic 0.98 mm2 solar harvester is presented. Using only the pn-junctions of the standard 130 nm single n-well process, the monolithic harvester can serve as supply for wireless sensor grains. Based on the perturbation and observation method, the MPPT algorithm maximizes the output current of the integrated charge...
In this paper a low power amplifier for bio-signal acquisition is described. The design takes benefit of UTBB-FDSOI 28nm technology and exploits bulk under the buried oxide as a second gate of FET device. This amplifier exhibits low supply current of 25nA, while keeping input noise at 24 µV in bio-signal frequency band. The gain of the amplifier is 71dB.
This work presents a fully differential operational amplifier (opamp) design architecture, that achieves a high gain bandwidth at a low power consumption. For verification, the architecture is implemented in a low cost 180 nm bulk CMOS technology. The chip achieves a high gain bandwidth of 2.03 GHz at 55° phase margin with a low power consumption of only 2.25 mW. Of course even better results are...
A 110nA quiescent current (IQ) buck converter for ultra-low power application is presented. A novel zero IQ pull-down structure, which consists in native NMOS and PJEF, is proposed to achieve zero-power supply monitor and save the total IQ. Implemented in 0.35um CMOS process, the converter realizes 78% efficiency in 1uA load and over 90% for load range from 5uA to 100mA. With adaptive-bias hysteresis...
Power loss at the output stage of conventional constant current neural stimulators is notably high. This is particularly disadvantageous for applications in implantable systems where power budget is limited. We present a novel electrical stimulator architecture for significantly reduced power loss and low noise operation. The system generates a calibrated output voltage profile for driving electrode...
A 3.1 nJ/bit pulsed millimeter-wave transmitter, 300μm by 300μm by 250μm in size, designed in 32-nm SOI CMOS, operates on an electric potential of 130mV and 3.1nW of dc power. These achieved power levels and potentials are comparable to those present across cellular and intracellular membranes. Far-field data transmission at 33 GHz is achieved by supply-switching an LC-oscillator with a duty cycle...
This paper presents an ASIC design of ultra-low power SAR ADC. To achieve ultra-low power, the proposed ADC operates at ultra-low voltage, deploying a single-ended structure and top plate sampling technique. In order to improve sampling circuit linearity at ultra-low supply voltage, a bootstrapped switch is developed. A non-binary redundant algorithm is applied to correct the inevitable decision errors...
This paper presents an embedded DRAM memory design on 32 nm Low Power process using recently introduced Capacitor Over Low-K (COLK) bitcell architecture. It consists in the 1st functional silicon demonstration of 32 nm embedded DRAM macrocell with unrivalled density of O.lmmVMbit. The memory features a high performance sense amplifier with tunable reference level, an overdriven reliability-friendly...
This paper presents a low-power speed-scalable 8bit Successive Approximation Register (SAR) ADC implemented in 0.18-μm CMOS. By designing a compact asynchronous controller and a charge-sharing DAC, the power consumption can be linearly scaled with the conversion speed. A maximum power dissipation of 28.4 μW and 0.019 mm2 total area make this ADC ideal for highly integrated wireless sensor nodes. The...
A highly manufacturable embedded DRAM technology at 40 nm node is presented. This report provides the characterization data of 128 Mbit embedded DRAM test vehicle fabricated by 40 nm eDRAM 200 MHz low power process. The test vehicle is composed of 32 macros and each macro unit is 4 Mb with configuration 32 k × 128 bits. The process is cost effective and compatible to our low power Logic core process...
High switching frequencies (several MHz) allow the integration of low power DC/DC converters. Although, in theory, a high switching frequency would make possible to implement a conventional voltage mode control with very high bandwidth, in practice, parasitic effects and robustness make very complex to achieve bandwidths higher than 1MHz. This paper proposes a fast control technique to optimize the...
Performance, efficiency, cost of the power converters and their associated control, are important considerations for the commercialization of renewable power sources. In view of this, this paper proposes a reliable and low cost power electronics interface for photovoltaic energy systems, using a single DSP controller. The proposed approach achieves the following: (a) integrate the dc-dc converter...
The energy consumed in switching the voltage on the power rail (VDD switching energy) is a significant overhead in systems using Dynamic Voltage Scaling (DVS) and/or power gating. In this work we propose and demonstrate the use of Stepped Supply Voltage Switching (SVS) for reducing VDD switching energy. We show the analysis, benefits, and overheads of using SVS for DSP algorithms implemented with...
Applications such as sensor networks and medical monitoring often require ADCs that can digitize signals with varying bandwidth and dynamic range requirements. In energy-constrained systems, it is beneficial to adapt the ADC performance to the signal to avoid consuming power on unnecessary bandwidth or accuracy. Therefore, this paper presents a single reconfigurable SAR ADC whose power scales with...
Recently it has been shown that frequency-translated BPFs offer high-Q filtering with their center frequency precisely controlled by a clock. To address the scalability concerns and to achieve the same level of integration as the zero or low-IF receivers, this paper propose a low-power process-scalable superheterodyne receiver with integrated high-Q filters. The receiver presented exceeds the requirements...
These tutorials discuss the following: Integrated LC oscillators; Embedded Memories for SoC: Overview of Design, Test, and Applications and Challenges in the Nano-Scale CMOS; Ultra Low-Power and Low-Voltage Digital-Circuit Design Techniques; Layout - The Other Half of Nanometer Analog Design; DPLL-Based Clock and Data Recovery; Practical Power-Delay Design Trade-offs; Distortion in Cellular Receivers;...
In this paper, a second-order 14 bit 2MSPS sigma-delta ADC used for data acquisition is proposed. The adopted feed-forward structure in SDM has reduced more than 50% output swing of integrator, leading to inherent low power operation compared with the conventional feedback topology. The proposed ADC, designed in TSMC 0.18μm CMOS technology, achieves 83.9dB peak SNR and 91dB SFDR with an over sampling...
This paper describes the modeling and design considerations of a low-power divide-by-two injection-locked frequency divider (ILFD) for 60GHz frequency synthesizer applications implemented in 90nm CMOS process. The paper proposes a divider's locking range model based on mixing analysis. The design uses a capacitor bank for the divider band selection and tail current injection. Measured results of the...
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