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A new approach blends a new camera architecture based on a digital micro-mirror device with the new mathematical theory and algorithms of compressive sampling. The “single-pixel” compressive digital camera functions by the method of focussing the desired image onto a digital micro-mirror device (DMD) consisting of an array of N tiny mirrors. Camera architecture employs a digital micromirror array...
This paper presents FPGA based VGA display interface design for image display verification during test procedure in the star sensor debugging phase. Methods of asynchronous FIFO, methods for data update during line blanking interval and vertical blanking interval were adopted, and CCD camera's requirements for special sequential order were satisfied, and the metastable state problem caused by data's...
This paper presents design tutorials on image and audio signal processing for an introductory digital systems course. The objectives are to introduce advanced design and to promote interest in digital systems. The use of audio and visual components of design can enhance student's hands-on learning. By using co-simulation, a method in which software in a numerical computation environment generates...
The paper designs a common image acquisition system for digital cameras with Camera Link interface. The system uses CMOS image sensor of 1.3 million pixels as the light-sensitive chip and high-performance FPGA as the main controller. In order to meet ease of use and high real-time demands, the system uses high-speed USB2.0 interface to transfer image data between the acquisition system and PC. Further...
We discuss FPGA implementations of object (such as face) detectors in video streams using the accurate Haar-feature based algorithm. Rather than creating one implementation for one FPGA, we develop a method to generate a series of implementations that have different size and performance to target different FPGA devices. The automatic generation was enabled by custom design space exploration on a particular...
Digital halftoning is a crucial technique used in digital printers to convert a continuous-tone image into a pattern of black and white dots. Halftoning is used since printers have a limited availability of inks and cannot reproduce all the color intensities in a continuous image. Error Diffusion is an algorithm in halftoning that iteratively quantizes pixels in a neighborhood dependent fashion. This...
This paper proposes a wireless communication system for secure transmission of data. Bluetooth is used as the wireless communication medium due to its low-cost and low-power consumption features. Advanced encryption standard (AES) protocol is implemented for the security reason over Bluetooth stack. RC10 prototyping board with Xilinx XC3S1500L-4-FG320 device has been used for the hardware evaluation...
A novel hardware implementation of an omnidirectional image sensor is presented which is capable of acquiring and processing 3D image sequences in real time. The system consists of a hemispherical arrangement of a large number of CMOS imagers, connecting to a layered arrangement of a high-end FPGA platform that is responsible data framing and image processing. The hardware platform in charge of real-time...
Face recognition systems play a vital role in many applications including surveillance, biometrics and security. In this work, we present a complete real-time face recognition system consisting of a face detection, a recognition and a downsampling module using an FPGA. Our system provides an end-to-end solution for face recognition; it receives video input from a camera, detects the locations of the...
Biological vision systems use saliency-based visual attention mechanisms to limit higher-level vision processing on the most visually-salient subsets of an input image. Among several computational models that capture the visual-saliency in biological system, an information theoretic AIM(Attention based on Information Maximization) algorithm has been demonstrated to predict human gaze patterns better...
The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this paper, we use OpenCL, an industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our architectural synthesis tool, SOpenCL (Silicon-OpenCL), adapts OpenCL into a novel...
In this paper, different kinds of methods for realizing gray scale for LCoS were studied. Among these methods, time ratio gray scale (TRG) is superior to other methods in the aspect of gray scale. We have achieved high gray scales and image uniformity for the LCoS using the sub-frame modulation of TRG. In this method, each frame was divided into 8 sub-frames with the proportion as 1:2:4:8:16:32:64:128...
This paper presents a design method of infrared image display card using FPGA and ADV7123. Its main function includes pixel gray level conversion, image zoom in and PAL standard video signal generation. The design ideals, hardware architecture, FPGA logical modules, FPGA configuration, interconnection between display card and master board, and the PAL standard video signal generation method using...
Through our work we managed to operate a display which has 480×272 resolution and 16 bit color depth with an FPGA equipped with an sbRIO 9632 developer card. The program was written in LabView and rotates a cube. With this work we managed to rotate a cube in 3D, create a 2D image from it with central projection, and then visualize it on the display, all of this on FPGA. The connection between the...
In this paper, we present the design and implementation of an efficient hardware architecture for VGA monitor controllers based on FPGA technology. The design is compatible with PLB bus and has a high potential to be used in Xilinx FPGA-based systems. The ability to provide multiple display resolutions (up to WXGA 1280×800) and a customizable internal FIFO make the proposed architecture suitable for...
MPEG is one of the popular standards in image compression. Blocking is the most annoying artifact of encoding/decoding process. In this paper a post-processing deblocking algorithm for MPEG video stream is proposed. This method is based on the correlation of local pixels in block boundary region. It takes two 4×4 adjacent small blocks on both sides of a block boundary as a local processing region...
In this paper, we present an approach that uses information about the FPGA architecture to achieve optimized allocation of embedded memory in real-time video processing system. A cost function defined in terms of required memory sizes, available block- and distributed-RAM resources is used to motivate the allocation decision. This work is a high-level exploration that generates VHDL RTL modules and...
SIFT (Scale Invariant Feature Transform) is one of most popular approach for feature detection and matching. Many parallelized algorithms have been proposed to accelerate SIFT to apply into real-time systems. This paper divides the researches into three different categories, that is, optimizing parallel algorithms based on general purpose multi-core processors, designing customized multi-core processor...
Currently the market and the academic community have required applications of image and video processing with several real-time constraints. In order to seek an alternative design that allows the rapid development of real time image processing systems this paper proposes an unified hardware architecture for some image filtering algorithms in space domain, such as windowing-based operations, which...
Mathematical morphology supplies powerful tools for low level image analysis, with applications in many areas. In this paper, the development of a novel reconfigurable hardware using a genetic algorithm and a pipeline architecture is proposed for the task of shape recognition in binary images. For the recognition process, a large sized convex structuring element representing the object shape to be...
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