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Video de-interlacing techniques, which convert the format of interlaced images to progressive images, are important today to improve the quality of display. Motion adaptive de-interlacing techniques are capable of improving the quality of the visual results. Most of them focus on the static or horizontal motion detection only; nevertheless, their performances are also affected by vertical motion....
In this paper, we proposed two novel low power multiplier designs based on improved column bypassing schemes. The power saving comes from bypassing signals along those adder columns in the array multiplier corresponding to zero bits in the multiplicand. Spurious signal switching activities can then be eliminated when bypassing occurs. The proposed designs successfully resolve the adverse DC power...
In this paper, we present an EDA tool for automatic generation of parallel CRC and parallel scrambler designs subject to different generator polynomials and parallel processing rates. The base architecture is derived from a state space transform scheme with fully pipelined pro- and post-processing blocks and the critical path is limited to 1 XOR delay only. The maximum input data width for CRC and...
A novel full adder design with only 10 transistors is presented targeting low power arithmetic operation for wireless base band processing. To alleviate the multi threshold voltage loss and the speed degradation problems common in 10T full adder designs, an inverter is successfully embedded along the carry path at no extra circuit overhead. It helps restore the logic swing and thus the driving capability...
In this paper, we propose an interface design which supports serial-link packet-based transmission model for network-on-chip application The interface function consists of packet construction, flow control, error detect, re-transmission mechanism, data scrambler and 8b/10b transformation. The whole function is partitioned into three layers and designed as a peer-to-peer architecture. Every layer can...
A film-to-video conversion technique with scene cut detection is proposed and its performances are examined. Scene cut happens fairly often in film broadcasting and it tends to destabilize the quality of performance while motion compensated interpolation technique is utilized. In the proposed method, the scene cut detection is executed at the first stage of motion compensation of frame-to-video conversion...
In this paper, we propose a low complexity full adder design (10-transistor per bit) featuring higher computing speed, lower operating voltage, and lower energy consumption compared with peer designs. The design adopts inverter buffered XOR/XNOR designs to alleviate the threshold voltage loss problem, which often prevents the full adder design from low supply voltage operation and from direct cascading...
This paper presents an efficient video de-interlacing technique with scene change detection and its VLSI architecture design. Scene changes happen quite often in film broadcasting and they tend to destabilize the quality of performance such as jagged effect, blurred effect, and artifacts effect, while de-interlacing technique is utilized. Therefore, the issue of scene change needs to be addressed...
An efficient video de-interlacing technique with scene change detection is proposed and its performances are examined. Scene changes happen quite often in film broadcasting and they tend to destabilize the quality of performance such as jagged effect, blurred effect, and artifacts effect, while de-interlacing technique is utilized. Therefore, the issue of scene change needs to be addressed with de-interlacing...
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