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Multi-wall carbon nanotubes (MWNTs) have potentially provided an attractive solution over single-wall carbon nanotube (SWNT) bundles at deep sub-micron level very large scale integration (VLSI) technologies. This paper presents a comprehensive analysis of propagation delay for both MWNT and SWNT bundles at different interconnect lengths (global) and shows a comparison of area for equivalent number...
This paper presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method has been used to reduce inter-wire coupling which is primary source of power dissipation, crosstalk and delay in coupled interconnects. The proposed method focuses on simplified and improved circuit of encoder for 4, 8 and 16 coupled...
Process variation is considered to be a major concern in the design of circuits including interconnect pipelines in current deep submicron regime. Process variation results in uncertainties of circuit performances such as propagation delay. The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-100-nm scale. The reduced predictability can be attributed...
This research work proposes an improved algorithm to extract maternal heart rate from an ECG measured of the mother's abdomen. Recently various research efforts have been devoted to this field. The most recent ones include filtering and threshold methods, wavelet methods, neural networks and others. Each of these methods has different effectiveness and weaknesses. In spite of the fact that their performance...
Every communication receiver that uses in-phase and quadrature channel signal processing technique encounters problems related to matching of gain and phase in both the channels. The gain and phase imbalances occur between Low Pass Filter and Local Oscillator used in both the channels and as a result the performance of the receivers and the quality of the received signals are degraded. The imbalances...
Polymeric Thin Film Transistors (PTFTs) have undergone extraordinary improvements during the last decade. PTFTs which are also termed as Organic Thin Film Transistor (OTFT) are promising devices for future development of variety of low-cost and large-area electronics applications such as active-matrix displays and flexible micro-electronics. Organic transistors show high mobility, high-speed and high-current...
This paper deals with the design and analysis of Ternary Content Addressable Memory using 180nm technology. The main aim of the TCAM is to perform the search operation using match line (ML). Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network...
In DSM technology and beyond, the performance and correctness of the circuit cannot be assured without taking into consideration the multiple effects of interconnect parasitics. The inter wire parasitics i.e. mutual inductance and coupling capacitance are primary sources of crosstalk noise. In this paper, the optimization of coupling capacitance for delay and peak noise is carried out qualitatively...
This paper analyzes the effect of driver size and number of shells on propagation delay for Multi-Walled Carbon Nanotubes (MWCNT) interconnect at 22nm technology node. An equivalent circuit model of MWCNT is used for estimation and analysis of propagation delay. The delay through MWCNT and Cu interconnects are compared for various driver sizes and number of MWCNT shells. The SPICE simulation results...
Now-a-days various Digital Signal Processing systems are implemented on a platform of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be such kind of programmable signal processor. In recent times, it has been a widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications...
Electrical conduction behavior of pristine and iodine doped polyetherimides (PEI) has been investigated under both transient and steady state conditions in the operating temperature range 50–200°C at various electric fields of 12–60 kV/cm. The transient currents show the hyperbolic decay character, and the decay exponent p (a measure of current decay rate) decreases with temperature (T) and doping...
For System on-chip (SoC) designs in current Deep Submicron (DSM) era, interconnects play important role in overall performance of the chip. The factors such as propagation delay, power dissipation and crosstalk through RC modeled interconnects substantially affects the entire working of the chip. Functional crosstalk and crosstalk induced propagation delay have recently emerged as major sources of...
Digital Signal Processing (DSP) system involves a wide spectrum of DSP algorithms for its realization and is often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented on a variety of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be widely researched topic...
The shrinking feature size of MOSFET devices is largely responsible for growth of VLSI circuits. In DSM technology below 0.18 μm, interconnect parasitics are significant and erupt as performance limiting parameters of the circuit. Because of short spacing between interconnects, faster signal rise time, longer wire length and use of low K-dielectric material, the coupling capacitance (CC...
The paper aims to analyze the effect of crosstalk in dual aggressor environment. The extent of crosstalk noise with the increment in the interconnect length is observed. It also observes the effect on delay with the gradual increment in the interconnect length and extent of reduction in crosstalk voltage on repeater insertion. A three wire multiline model is considered.
A method is proposed here for development of a new tool which provides fast and efficient way for fault diagnoses in analog CMOS circuits arises due to glitches. The tool follows SBT (simulation before testing) based approach for tests the CMOS analog circuits against faults arises due to glitches. SBT system for fault diagnosis requires some form of a fault dictionary to which the test data is compared...
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper provides a comprehensive overview of the types and sources of all aspects of process variations in driver -interconnect-load system. The primary sources of manufacturing variation include Deposition, Chemical Mechanical Planarization (CMP), Etching, Resolution Enhancement...
Over the past years complexity of PCB board and the surface mount technology has increased by leaps and bounds. This limits the use of traditional in-circuit test techniques for testing of such boards. This paper addresses the various issues of board level interconnect testing using Boundary Scan architecture. This work implements BIST using Boundary Scan technique. A new Algorithm is developed to...
This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially the existing SRAM architectures are investigated, and thereafter a suitable basic 6T SRAM structure is chosen. The key to low power dissipation in the SRAM data path is to reduce the signal swings on the highly capacitive nodes like the bit and data lines...
In DSM technology, unintended interactions between signals propagating through interconnect turn out to be critical design concern. At technology nodes below 0.25μm, the performance and correctness of a design cannot be assured without considering noise effects. In integrated circuits, the main cause of signal integrity problems is crosstalk. This paper presents the effects of aggressor driver width...
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