This paper analyzes the area efficiency of the mapping of interconnection networks for parallel processing on one form of uniform massively parallel architecture of the cellular type. This architecture is meant to model one trend in the advanced sea-of-gates VLSI. The analytical analysis was done for the mapping area of eight different types of interconnection networks which, according to a widely accepted classification, belong to all major interconnection network classes. In the domain of analytical analysis, formulas were derived that show the VLSI area necessary for mapping each chosen type of interconnection network. Major results of this research are the formulas for the number of cells necessary to realize a network. These formulas show, in some cases, significant structural differences in comparison with the formulas that imply classical implementations. This is because the critical issue for the technology under consideration here is the number of two-dimensional VLSI cells, and for the classical technology the critical issue is the number of interconnection wires being routed in a three-dimensional space.