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A reprogrammable hardware platform is used for the co-design and implementation of a computational intensive mathematical problem, namely the listing of irreducible polynomials over Galois fields of order 3 (GF(3)), The main goal is to accelerate the performance compared to an existing software implementation. This project uses hardware/software co-design methodologies and techniques, and it is completely...
Today's digital systems design requires extensive system- level simulation to ensure that the right architectural trade-offs are made. In platform based designs a large number of platforms models must be executed for tuning the platform for the application. In order to run these simulations with adequate performance, design architects have increasingly employed abstract transaction-level models instead...
A widely used approach to avoid network intrusion is SNORT, an open source network intrusion detection system (NIDS). This work describes SPP- NIDS, a architecture for intrusion detection supporting SNORT rules. SPP-NIDS is attractive to real-world network intrusion detection, due to its scalability, flexibility and performance features. A parameterizable cluster of simple processors provides system...
Networks-on-chip, or NoCs, are one communication architecture candidate to be used in present and future SoCs, due to its scalability, reusability and performance. The focus of this paper is the analysis of IP communication models in NoCs. Employing standard external interfaces, as OCP, is recommended to enable the use of NoCs by different IP core providers. The second point related to reusability...
In this paper we present the design flow for a fractional-N (frac-N) frequency synthesizer proto type from the system level conceptualization of the PLL to its hardware implementation. The prototyping hardware consists of a of frac-N PLL IC designed in TSMC 0.18 mum mixed signal/RF CMOS process mounted on a RF prototype impedance controlled board. The RF board is interfaced to a digital delta sigma...
In this paper, we propose a novel FTL (flash translation layer) architecture for NAND flash based applications such as mp3 players, DSCs (Digital still camera) and SSDs (Solid-state disk). Even though the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, its efficient algorithms have a significant impact on performance as well as lifetime...
Modern application specific instruction-set processors (ASIPs) face the demanding task of delivering high performance for a wide range of applications. For enhancing the performance, architectural features e.g. pipelining, VLIW etc are often employed in ASIPs, leading to high design complexity. Integrated ASIP design environments like templated-based approaches [1] and language- driven approaches...
We have presented a formal set of synchronization components called synchronizers for refining synchronous communication onto HW/SW codesign architectures. Such an architecture imposes asynchronous communication between HW-HW, SW-SW and HW-SW components. The synchronizers enable local synchronization, thus satisfy the synchronization requirement of a typical IP core. In this paper, we present their...
We extend a model based development approach for software components of embedded systems by a model based testing framework. We motivate by describing challenges a developer has to face when developing embedded software and present as a solution an UML-centric development approach. We introduce a testing framework that allows specification of test cases for UML class models using UML sequence- and...
Transactional memory (TM) is an emerging synchronization mechanism that aims to solve most of the difficulties inherent in lock-based approaches. TM implementations may either rely on special hardware (HTM) or employ a software-only (STM) technique. While STM can be implemented and evaluated in current machines, HTM requires hardware modification and a prototyping infrastructure. We present in this...
Designing security softwares that evolve as quickly as threats is a truthful challenge. In addition, current software becomes increasingly more complex and difficult to handle even for security experts. Intrusion Detection Softwares (IDS) represent a solution that can alleviate these concerns. This paper proposes a framework to automatically build an effective online IDS which can check if the program's...
This paper presents the design and implementation of a real time face detection system on an embedded reconfigurable platform. Our approach to face detection is based on a skin-segmentation algorithm followed by feature extraction and face verification. Our implementation is done on DMV, a reconfigurable platform with novel features targeting real time computer vision applications. DMV is a system...
In this paper we discuss how one of the most famous local optimization algorithms for the Traveling Salesman Problem, the 2-Opt, can be efficiently implemented in hardware for Euclidean TSP instances up to a few hundred cities. We introduce the notion of "symmetrical 2-Opt moves" which allows us to uncover fine-grain parallelism when executing the specified algorithm. We propose a novel...
Formal property specification and model checking are increasingly deployed in the HW design industry, thanks to the emergence of standard property specification languages and major advances in the maturity of model checking tools. Moderately sized HW IP is now within the capacity of such tools. Complete formal verification of such IP requires not only efficient algorithms, but also a systematic approach...
This paper addresses the need for formal specification and runtime verification of system-level requirements of distributed reactive systems. It describes a formalism for specifying global system behaviors in terms of message sequence chart assertions and a technique for the evaluation of the likelihood of success of a distributed protocol under non-trivial communication conditions via discrete event...
Multi-processors systems-on-chip (MPSoCs) are becoming increasingly popular in embedded systems for the high degree of performance and flexibility they permit. While most MPSoCs are today highly heterogeneous for better fitting the target applications, homogeneous systems may become in a near future a viable alternative bringing other benefits such as run-time load balancing. The work presented in...
Partial run time reconfiguration (pRTR) enables a dynamic replacement of design modules to optimize the resource utilization of FPGA-based hardware emulation. This requires an appropriate partitioning of the entire design into particular hardware modules. There exist various methods to partition a design at functional as well as at structural level. In this paper, an adapted functional method to partition...
UML-RT is a UML real-time profile that allows event-driven and distributed systems. UML-RT is not a formal specification language, therefore it is not possible to do formal verification of UML-RT models. This article proposes formal semantics for UML-RT via mapping of UML-RT communicating elements into pi-calculus. The pi-calculus is a process algebra to model concurrent systems. A prototype was also...
Multimedia applications require heterogeneous multiprocessor architectures with specific I/O components in order to achieve computation and communication performances. The different processors run different software stacks made of the application code and the hardware dependent software layer. Developing this software usually makes use of a high level programming environment that does not handle specific...
As embedded systems are getting more complex, they are also presenting more stringent constraints like performance, power consumption, memory footprint and so on. At the same time, because of market pressures, their development time must be constantly reduced. The employment of object orientation would solve the design cycle problem. However, OO languages like Java or C+ + are not targeted to any...
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