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A discrete time single loop 2nd order 5-bit ΔΣ modulator is implemented in 65nm CMOS for digital audio and sensor applications. We propose a power efficient integrator based on periodical-reset dynamic amplifier without static current consumption. A passive inter-stage sampling method is proposed which prevents active buffer. A 3-D capacitance layout implementation method is employed to saving the...
This paper presents a power-efficient 100-MS/s, 10-bit asynchronous successive approximation register (SAR) ADC. It includes an on-chip reference buffer and the total power dissipation is 6.8 mW. To achieve high performance with high power-efficiency in the proposed ADC, bootstrapped switch, redundancy, set-and-down switching approach, dynamic comparator and dynamic logic techniques are employed....
ESD sensitive test was performed to verify the design of circuit protection unit. The failure ICs were analyzed by OBIRCH technique. Three anomalous thermally sensitive sites were localized including I/O and VCCIOs. OBIRCH analysis confirmed the failure sites were directly connect to the pads, mostly ESD protection units, decoupling capacitor and internal inverter. Physical failure analysis confirmed...
In older to show the failure phenomena of breakdown spot caused by a small energy voltage for metal-insulator-metal (MIM) capacitors failure analysis in GaAs integrated circuit, different methods of de-golding technology was discussed in this paper. A kind of de-golding solution was optimization with consideration of MIM capacitors' construction and material. Typical MIM capacitor failure analysis...
This paper presents a single loop 3rd order 5-bit audio ΣΔ modulator with feed forward path. Feed forward technology relaxes the amplifier design requirement by reducing output swing of the integrators. Chopper stabilization technology is employed to mitigate the flicker noise introduced by 1st integrator. A kind of asynchronous successive approximation (SAR) quantizer without extra fast clock replaces...
This paper presents a discrete time ΔΣ modulator operating under 1V power supply. To achieve high precision under low voltage while preserve low power consumption, techniques from systematic level to circuits' level are used. On the systematic level, modulator with 4-bit quantizer is employed. The advantage is its excellent stability performance which extends input signal range near to the reference...
In this paper a 1V 15-bit ΔΣ ADC for audio application is presented. Second order modulator with feed-forward path is adopted in order to reduce the swing of each integrator. Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is employed to save power. Decimation filter is implemented with seven-stage cascade sub-filters. Timing multiplexing and resource reuse methodology...
This paper presents a high precision multi-bit audio ΔΣ modulator working under IV supply. We propose a kind of asynchronous 4-bit successive approximation quantizer without fast clock generation. Feed-forward topology with digital summing is adopted to relax the amplifier design requirement. Power efficient single stage OTA is adopted to drive the large sampling capacitor with...
A single-loop second-order 3 bits ΔΣ modulator in 180 nm standard CMOS is presented. The design is intended to achieve high linearity in low-voltage low-power environment. The modulator achieves 89-dB SNDR and 98-dB SFDR in 20Hz~16kHz signal bandwidth, while the power consumption is 210 μW under 1-V supply voltage.
A 15-bit 3rd order ΔΣ modulator is presented. The feed forward topology with 18-level quantizer is adopted. The signal swing of the 1st integrator is effectively suppressed. A current-mirror OTA with 42dB DC gain is used in the 1st integrator. Chop stabilization is employed to remove the flicker noise. The prototype is fabricated in 0.18μm CMOS. The active die area is 0.85×0.85mm2. The power consumption...
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