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This paper presents a parallel arithmetic coding scheme in which supports a large degree of parallelism with a marginal cost in terms of the coding efficiency. The parallelism is brought by coding the bits using multiple arithmetic coders. We identify two types of losses in coding efficiency by breaking the dependency among the data: the loss by breaking the probability prediction process and the...
As a new technique for low-power design and quantum computing, reversible logic has been paid much attention. A significant part of research lies in synthesizing a reversible network from non-reversible specification. However, current synthesis algorithms for reversible circuits suffer low efficiency and do not reach area optimization, so they are only applicable to small logic functions. In this...
This paper presents a new architecture of bang-bang phase frequency detector based on standard cells. The proposed architecture presents advantages in terms of compatibility with fully-automated design flow of digital circuitry compared with other architectures. The metastability failure is also studied. The reliability of this architecture is approved by simulation results in CMOS65 nm.
This paper discusses the mechanism behind dynamic jitter accumulation in clock repeaters, considering the impact of power supply noise correlations. We show that differential and common mode noise have a different impact on jitter accumulation, depending on correlations between cascaded repeater stages. We also propose a simple accumulation model that can be used to replace time-consuming transient...
Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establishing coherence and consistency for different types of shared memory by hardware means. Also support for...
In a Content Addressable Memory (CAM) architecture, both the match-line (ML) sensing circuit and the priority encoder (PE) contribute significantly large delays during a compare cycle. Meanwhile the priority encoder consumes significantly less energy when compared to the sensing circuits, i.e. ∼1% of the overall energy consumption. Based on this observation, we propose the use of dual-supply voltages...
Wireless sensor nodes require longevity, zero maintenance, and self-sufficiency. However, constraints on power, system volume, and cost are prohibitive to satisfy these requirements. In this paper, a reconfigurable energy management unit (EMU) is introduced that works within the constraints to meet the requirements. With multi-directional energy flow control, the EMU achieves the unification of photovoltaic...
Analog circuit designs are often biased to work in sub-threshold mode for low power constraints and for better gate-source voltage matching performances. Depending on process, hump effect may change MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. Actually, even without body effect, hump mainly degrades MOS matching performances in the sub-threshold area...
A new on-die temperature sensor that operates at low supply voltages and exhibits low process sensitivity and good linearity over a wide temperature range is introduced. When compared to conventional structures which have limited supply voltage headroom at the slow-n process corner, the new structures have sufficient headroom to practically operate well over all process corners. When implemented in...
This paper shows the development of a measurement system for transportation purposes based in triaxial accelerometers and Global Positioning Systems (GPS) that allow the measurement of acceleration events produced by fast driving or floor's structures or defects as holes, speed bumps or among others and to report the geographic position where the event occurred through the GPS module. Finally, the...
Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm circuits and beyond. An on-chip metastability measurement circuit was fabricated in a 65nm 1.1V bulk CMOS. A fully digital on-chip measurement system is presented here that helps to characterize synchronizers in future technologies. Different...
This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks. The VLSI implementation of the network...
Motion compensated prediction (MCP) plays an important role in video coding due to its great capability of reducing temporal redundancy. In this paper, we propose a new MCP scheme by adaptive patch matching with the full use of the reconstructed pixels surrounding the current block (referred to as the template inside the patch) aiming at achieving a more accurate prediction than conventional MCP....
Recently, the investigation of the cognitive radio (CR) system is actively progressed as one of the methods for using the frequency resources more efficiently. In CR systems, when the frequency band allocated to the incumbent user is not used, the unused frequency band is assigned to the secondary user. Thus, the FFT input signals corresponding to the actually used frequency band by the incumbent...
A digitally controlled resonant tank oscillator with loop antenna radiating inductor offers high energy efficiency in BFSK transmission, however suffers from frequency drift. Here we present a fast-settling adaptive digital architecture for dual-loop frequency locking of a BFSK transmitter. The method uses interleaved frequency-locked loops (FLL) that allow fast and energy-efficient direct digitally...
Wind energy generation systems are major components of distributed generation units or micro-grids. Application of the doubly fed induction generator (DFIG) in wind energy generation systems allows variable speed operation by using partially rated back-to-back quadruple active and reactive power PWM converters. The control of the system is very complex. Many new control schemes reported in the literature...
A novel technique is presented for finite-wordlength (FW) particle swarm optimization (PSO) of BIBO stable FRM digital filters incorporating bilinear-LDI IIR interpolation subfilters. A novel LUT scheme is developed to ensure that the FWPSO automatically searches over permissible FW multiplier coefficient values only in the course of optimization. The salient feature of the proposed LUT scheme is...
This paper presents an improved design for a Level-Crossing ADC (LCADC) that incorporates both an equivalent-time method and a clocked comparator. The LCADC is experimentally validated using a 65 nm clocked comparator.
A new digitally-controlled exponential variable gain amplifier is presented in this paper. This circuit is based on the proposed novel method of expanding the dynamic range over which a traditional approximate function estimates the ideal exponential function. The technique is unique in a way that it culminates in a true exponential amplifier over an improved input dynamic range. Tuning in this circuit...
The design of a low-power low-voltage programmable temperature detection circuit is described. The circuit provides a digital output that signals over-temperature and under-temperature conditions when die temperature rises above or falls below the programmed temperature thresholds. The output is obtained from the comparison between two temperature-related signals; the former has a CTAT with fixed...
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