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A source-switched charge pump (SSCP) with reverse leakage compensation technique is proposed to reduce spur level of wideband PLL induced by the reverse sub-threshold leakage of the charge pump. This technique can set the source–drain voltage of current-source N-type MOS (NMOS)/P-type MOS to be close to zero at off-state of the charge pump and thus reduce the reverse leakage. Compared with the conventional...
A fractional-N PLL for multi-standard transceiver is presented. The tuning range covers dual bands of 0.38∼6GHz and 9~12GHz. A high-speed ultra-band divide-by-2 circuit is designed to accomplish the frequency band of 0.3 to 13.7GHz. A novel high isolation multiplexer is presented to achieve the frequency band selection in LO paths. This chip was implemented with 65nm CMOS technology and the maximum...
In this paper a 1V 15-bit ΔΣ ADC for audio application is presented. Second order modulator with feed-forward path is adopted in order to reduce the swing of each integrator. Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is employed to save power. Decimation filter is implemented with seven-stage cascade sub-filters. Timing multiplexing and resource reuse methodology...
A nanopower subthreshold bandgap reference with 30ppm/°C from −30°C to 150°C has been implemented in 0.18µm CMOS. This design is based on weighted ΔVGS and is free of resistors. The major advantage of this design is that with nanopower consumption, the temperature range is extremely wide. To achieve high performance of subthreshold bandgap operating in high temperature (above 80°C), a leakage current...
This paper presents a high precision multi-bit audio ΔΣ modulator working under IV supply. We propose a kind of asynchronous 4-bit successive approximation quantizer without fast clock generation. Feed-forward topology with digital summing is adopted to relax the amplifier design requirement. Power efficient single stage OTA is adopted to drive the large sampling capacitor with...
A single-loop second-order 3 bits ΔΣ modulator in 180 nm standard CMOS is presented. The design is intended to achieve high linearity in low-voltage low-power environment. The modulator achieves 89-dB SNDR and 98-dB SFDR in 20Hz~16kHz signal bandwidth, while the power consumption is 210 μW under 1-V supply voltage.
A 15-bit 3rd order ΔΣ modulator is presented. The feed forward topology with 18-level quantizer is adopted. The signal swing of the 1st integrator is effectively suppressed. A current-mirror OTA with 42dB DC gain is used in the 1st integrator. Chop stabilization is employed to remove the flicker noise. The prototype is fabricated in 0.18μm CMOS. The active die area is 0.85×0.85mm2. The power consumption...
A 1.1 mW 87 dB dynamic range 3rd order ΔΣ modulator is implemented in 0.18 μm CMOS technology for the audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed and only one simple current mirror single-stage OTA with 34 dB DC gain is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB...
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