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A low power interface circuit for multisensory system is presented in this paper. A SAR capacitance-to-digital converter (CDC) and a SAR analog-to-digital converter (ADC) are combined together so that capacitance or voltage from different sensors can be measured by the same circuit and converted to digital signal directly. A dynamic comparator with self-calibration is designed to achieve zero-static...
In this paper a 1-V supply, 15-bit ADC design for audio applications is presented. The second order CIFB modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function (NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification...
This paper presents a discrete time ΔΣ modulator operating under 1V power supply. To achieve high precision under low voltage while preserve low power consumption, techniques from systematic level to circuits' level are used. On the systematic level, modulator with 4-bit quantizer is employed. The advantage is its excellent stability performance which extends input signal range near to the reference...
In this paper a 1V 15-bit ΔΣ ADC for audio application is presented. Second order modulator with feed-forward path is adopted in order to reduce the swing of each integrator. Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is employed to save power. Decimation filter is implemented with seven-stage cascade sub-filters. Timing multiplexing and resource reuse methodology...
This paper presents a high precision multi-bit audio ΔΣ modulator working under IV supply. We propose a kind of asynchronous 4-bit successive approximation quantizer without fast clock generation. Feed-forward topology with digital summing is adopted to relax the amplifier design requirement. Power efficient single stage OTA is adopted to drive the large sampling capacitor with...
A 15-bit 3rd order ΔΣ modulator is presented. The feed forward topology with 18-level quantizer is adopted. The signal swing of the 1st integrator is effectively suppressed. A current-mirror OTA with 42dB DC gain is used in the 1st integrator. Chop stabilization is employed to remove the flicker noise. The prototype is fabricated in 0.18μm CMOS. The active die area is 0.85×0.85mm2. The power consumption...
A 1.1 mW 87 dB dynamic range 3rd order ΔΣ modulator is implemented in 0.18 μm CMOS technology for the audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed and only one simple current mirror single-stage OTA with 34 dB DC gain is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB...
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