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Power consumption in a digital circuit increases significantly during test mode. The paper proposes a novel technique to minimize the peak power by circuit clustering based on distribution of energy among the scan cells. All the clusters are equally compatible with respect to the number of scan cells and total system energy which is equally divided among the clusters. The final energy of the system...
In this paper, we introduce a novel method to realize symmetric functions with reversible circuits. The key idea is based on a regular cascade tree structure of reversible gates that revel efficient realization of symmetric functions. The proposed structure uses low-cost reversible gates which reduce the overall circuit design cost and produces more arbitrary symmetric functions with a little increase...
Fault diagnosis is a complex and challenging problem in reversible logic circuits. The paper proposes a novel fault diagnosis technique for missing control faults in reversible logic circuits. The main focus of this technique is to extract the unique fault signature for each missing control fault in the circuit. The fault signatures are the sequences of test vectors to identify the location of the...
Ternary logic synthesis has a significant role to realize multi-input ternary logic functions. Balanced ternary logic that contains three states as -1, 0 and 1 has substantial advantage over standard ternary logic containing the logic states as 0, 1 and 2. The paper addresses the synthesis of balanced ternary reversible logic circuit and design of reversible half-adder and full-adder circuit by using...
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