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This paper presents a 28–32 GHz transceiver chip architecture in SiGe BiCMOS to meet the requirements of 5G phased-array communication links. An asymmetric design is employed for the transmit and receive paths to deliver an output P1dB of 8 dBm in TX mode and to achieve an input P1dB of 0 dBm in RX mode. The chip can operate with an external LO at 10–16 GHz and 20–28 GHz with the use of an on-chip...
This work presents a quad-core 28–32 GHz transmit/receive phased-array integrated circuit (IC) with flipchip packaging for 5G communication links. The IC consists of 4 Tx/Rx channels each with 6-bit phase and 14 dB amplitude control. The noise figure in the RX mode is 4.6 dB, the lowest reported to date to our best knowledge, and the output power in transmit mode is 10 dBm at P1dB. The power consumption...
This paper presents a 32-element phased-array architecture suitable for fifth-generation (5G) communication links. A 28–32 GHz silicon core chip is designed with 4 transmit/receive elements each with 14 dB gain control, 6-bit phase control, 4.6 dB measured noise figure (NF) in the RX mode and 10 dBm output 1 dB compression point (OP1dB) in the TX mode. Eight of these chips are flipped on a low-cost...
This paper presents a new harmonic rejection mixer (HRM) circuit that uses resistive scaling to achieve very high linearity and a harmonic rejection ratio (HRR) greater than 35 dBc. The mixer employs 4 double-balanced mixers driven by 8 LO phases with 12.5% duty cycle to isolate different paths. The mixer switches have been implemented with thin- and thick-oxide transistors to improve linearity further...
This paper presents a 6-bit active phase shifter using a new vector-sum method for X-band (8–12 GHz) phased arrays in 0.13 μm SiGe BiCMOS process. An RC filter is used to generate two orthogonal vectors which are then fed into four VGAs, two using the common-base and two using the common-emitter topology. This generates 4 vectors of 0°, 90°, 180° and 270° which are scaled and added by varying the...
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