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Caches are traditionally organized as a rigid hierarchy, with multiple levels of progressively larger and slower memories. Hierarchy allows a simple, fixed design to benefit a wide range of applications, since working sets settle at the smallest (i.e., fastest and most energy-efficient) level they fit in. However, rigid hierarchies also add overheads, because each level adds latency and energy even...
Last-level caches are increasingly distributed, consisting of many small banks. To perform well, most accesses must be served by banks near requesting cores. An attractive approach is to replicate read-only data so that a copy is available nearby. But replication introduces a delicate tradeoff between capacity and latency: too little replication forces cores to access faraway banks, while too much...
The use of multisource data in remote sensing image classification has become increasingly popular. Although additional features incorporated could improve classification accuracy, the amount of relevant information may induce interclass confusion. Feature selection plays an important role in image analysis process. This study investigates feature space optimization in the use of multispectral UltraCAM...
Cache hierarchies are increasingly non-uniform, so for systems to scale efficiently, data must be close to the threads that use it. Moreover, cache capacity is limited and contended among threads, introducing complex capacity/latency tradeoffs. Prior NUCA schemes have focused on managing data to reduce access latency, but have ignored thread placement; and applying prior NUMA thread placement schemes...
Network-on-Chip (NoC) systems achieve higher performance than bus systems for chip multiprocessor (CMP) systems. However, as the complexity of network increases, routing problems become performance bottlenecks. Conventional routings only use local or regional buffer occupancy (BO) information to choose a better path to deliver a packet. Due to lack of path diversity (PD) information, which is global...
The partially adaptive routing plays an important role in the performance of Network-on-Chip (NoC). It uses information of the network to select a better path to deliver a packet. However, it may have imbalanced path diversity in different directions, which makes their tolerances of traffic load differ a lot from each other. This characteristic would cause problems in traffic balancing but give us...
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