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A 25Gb/s heterogeneously-integrated Silicon-Photonic transmitter is designed entirely in CMOS, consisting of a high-swing driver wire-bonded to a MZ modulator. Measurement results demonstrate clean optical eye diagrams with > 4dB extinction ratio while consuming 0.52W.
A new asynchronous high speed multi-modulus divider (MMD) architecture is presented in this letter. This new architecture significantly reduces the delay of the critical path, which not only pushes to ultra-high speed operation, but also allows retiming techniques to suppress jitter accumulation from the divider chain simultaneously. A prototype in a 65 nm CMOS technology has demonstrated an improved...
A low power source-synchronous source-series-terminated (SST) transmitter (Tx) in 65 nm CMOS technology is presented. The Tx, comprised of nine data/control channels, a forwarded-clock channel and one PLL, merely dissipates 26.2 mW/channel while exhibiting a 750 mV differential eye height at 6.4 Gbps. The SST drivers can save ¾ output stage power of CML ones, and moreover, the proposed novel topology...
In order to avoid the complex adjustment of scaling factor and quantization factor in the design of fuzzy controller and the shortcomings that the fuzzy control rules can not be changed once identified, a fuzzy controller with self-optimizing rules is adopted . Particle swarm optimization (PSO) algorithm is used to optimize the parameters of fuzzy controller. A new evaluation function including the...
Godson-3A is a quad-core version of Godson-3 series which is a 174 mm2, 425 million transistors chip fabricated using 65 nm CMOS LP/GP process technology. It can be running at 1 GHz with less than 15 W power consumption. Large scale, high frequency, low power and tight time schedule make great challenges in the chip design. To overcome these challenges, a design methodology based on ASIC combining...
This paper presents the design of a 10 Gb/s low power wire-line transceiver in 65 nm CMOS process with 1 V supply voltage. The transmitter occupies an area of 430 mum times 240 mum, consumes 50.56 mW power and has a 5-order programmable pre-emphasis equalizer. The receiver occupies an area of 300 mum times 500 mum. With the novel half rate period calibration clock data recovery (CDR) circuit, the...
A sub-mA phase-locked loop fabricated in 65 nm digital CMOS process is presented. The impact of process variation is removed by an open-loop calibration that is performed only during the PLL start-up, which is opened during normal operation. The dual-loop PLL architecture is adopted to achieve process independent damping factor and pole-zero separation. A new phase frequency detector embedded with...
A clock system using PLL for high speed and low power parallel link is presented. The PLL is designed with a voltage regulator which provides a clear supply voltage for the noise sensitive blocks such as voltage controlled oscillator in the noisy environment. A new method is explored to generate clocks for dynamic frequency switching of the high speed link which works in source-synchronous style....
Considering the characteristics of mobile network, we import three important parameters: distribution density of mobile phone, coverage radius of Bluetooth signal and moving velocity of mobile phone to build an epidemic model of mobile phone virus which is different from the epidemic model of computer worm. Then analyzing different properties of this model with the change of parameters; discussing...
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