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This paper looks at a classical CMOS NOR-2 gate as well as Schmitt trigger (ST) versions, when the transistors are sized conventionally and unconventionally. ST gates exhibit positive feedback leading to better static noise margins (SNMs), hence less sensitive to noises (i.e., more reliable). The ST concept has lately been used for SRAM cells, with a few papers targeting digital logic. Here we explore...
This paper details preliminary results for a novel statistical analysis, using the delay of an inverter (the basic element of SRAM cells) as an example. The results obtained are statistically meaningful, and should allow for more accurate, faster, and better yield estimates.
This paper presents preliminary results of a statistical analysis of the SNM of inverters (as the basic element of any SRAM bit cell). Results are statistical meaningful as probabilities are calculated accurately, and should lead to more precise, faster, and better yield estimates. Comparisons with Monte Carlo simulations are supporting such claims.
This paper compares classical CMOS logic gates with their Schmitt trigger (ST) versions, when sized both conventionally as well as unconventionally. The reason for studying ST logic gates is due to their positive feedback which leads to hysteresis and, more importantly, to their better static noise margins (SNMs)—than classical CMOS logic gates. Obviously, the larger SNMs make ST logic gates less...
In this paper we advocate the use of nano-electro-mechanical switches (NEMS) to eliminate static power consumption, and propose a dual-voltage hybrid NEMS-CMOS scheme to also reduce dynamic power consumption. The main idea is to use a smaller voltage to propagate information, and a larger voltage to drive the NEMS. CMOS amplifiers are used to interface these two voltages. It follows that synthesizing...
Noises and variations are ubiquitous, but are still being ill-understood and in most cases treated simplistically, leading in most cases to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to ultra-low...
In this paper we propose a dual-voltage hybrid NEMS-CMOS scheme to reduce dynamic power consumption. The scheme uses a smaller input/output voltage to propagate information, and a larger voltage to drive (control) the NEMS. CMOS amplifiers are used to interface these two voltages. Gates with a large(r) number of inputs perform better, which matches the optimal NEMS circuit topology. Simulations for...
Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally...
This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (Vth) exactly (precise L's) and having...
This paper compares classical CMOS versus Schmitt trigger (ST) inverters (INVs), sized both conventionally as well as unconventionally. The reason is that ST INVs are using positive feedback (which leads to hysteresis) and are expected to exhibit much better static noise margins (SNMs) than classical CMOS INVs. That is why ST INVs are more reliable. Lately, quite a few papers have been looking at...
This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (Vth) exactly (leading to exact L's); (ii) more accurate...
Power consumption has been recognized as a grand challenge for nanoelectronics. With continuous scaling, wires (much more than devices) are going to be determining (almost entirely) the dynamic power: (i) their numbers are increasing exponentially, as each device needs a few wires; and (ii) they do not scale well, as their parasitic capacitances and RC-delays are not scaling in synch with device scaling...
By far the most daunting task facing nano-electronics are the wires, being at the heart of power/energy consumption, as: (i) their numbers are increasing exponentially (as each device needs a few wires); and (ii) they do not scale well for quite some time (their parasitic capacitances and RC-delays are not scaling in synch with devices). Innovations on both classical (i.e., based-on-wires, hence evolutionary)...
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