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A new method for reducing power and area of standard cell ASICs is described. The method is based on deliberately introducing clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: (1) the design of new differential flipflop, referred to...
This paper proposes a method to completely hide the functionality of a digital standard cell. This is accomplished by a differential threshold logic gate (TLG). A TLG with n inputs implements a subset of Boolean functions of n variables that are linear threshold functions. The output of such a gate is one if and only if an integer weighted linear arithmetic sum of the inputs equals or exceeds a given...
The paper presents an incremental electromagnetic (EM) simulator that is capable of simulating layout variants without compromising accuracy. Simulation efficiency in such situations typically is more than an order of magnitude faster than the initial solution of the same layout. This solver is also compatible with automated design flows in which a layout optimization tool creates design variants...
This paper presents a stable broadband rational modeling approach through adaptive frequency sampling for full-wave simulation. It is based on vector fitting with improved robustness and enhanced efficiency for multiple ports. Examples have shown that the adaptive frequency sampling strategy can reduce the cost of expensive calls to the full-wave solver significantly
The design of radio-frequency integrated circuits (RFICs) is highly sensitive to layout parasitics. In conventional methodologies, the layout parasitics are known only after the layout is complete and the schematic is resized to compensate for these parasitics. The drawback of such a methodology is that the convergence of this design iteration remains unpredictable. This paper proposes a novel synthesis...
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