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This paper introduces a thermal design method for 3D integration, using stacked thermal chips consisting of 100 polysilicon heaters in a 30 mm by 30 mm area on each chip to verify thermal models. For each heater, two levels of thermal load can be selected. Thermal effects from hot-spots in stacked chips were measured and verified in simulation results. Through this investigation, thermal models with...
This paper introduces a unique experimental setup of stacked thermal chips consisting of 100 polysilicon heaters in a 30 mm by 30 mm area. Temperature distributions in the stacked chips were measured and characterized with varying power in the heaters at a range exceeding 300 W in total; then thermal simulation models were built for 3D integration design.
An analysis of through silicon via (TSV) effects on next-generation super-high-speed transmission and power integrity package design for 2.5D modules with a highperformance central processing unit (CPU) or other 300A-class LSI mounted and 3D LSI is described in this paper.
Thermal design of 3D integration is one of most important issues for implementing this technology in applications. The lack of uniformity in micro-bump interconnection and high thermal resistance in BEOL (Back End of Line) in chips may limit the heat dissipation path for the cooling method. Firstly, in this study, through steady state measurement and FEM analysis of a F2F (Face to face) sample, which...
This paper provides a unique approach to thermal modeling of BEOL (Back End Of Line) layers in a 3D stacked LSI and introduces a novel cold plate design method by using a 30 mm by 30 mm LSI as an example. The paper focuses on BEOL thermal characterization, flow rate control in branch-channels and the micro-channels behind them in a cold plate in accordance with a power map of the LSI, and an experimental...
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