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Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a $3 \times 3$ TSV array, the severity of crosstalk noise in the center victim TSV is classified...
Series structures are inevitable and common in the design of digital logic gates. In this paper, to reduce the leakage power, we transplant the technique of mixed forward and reverse back-gate bias (mixed FBB/RBB) from FinFET forced stacks to the more widely-used series structures in FinFET logic gates. By employing the mixed FBB/RBB technique, the goal of leakage reduction is achieved without speed...
Setup time variation fault attacks that aim straightly at the FPGA devices have become hot spots nowadays. A high-efficient and accurate fault model aiming at FPGA-based cryptographic applications is proposed in this paper. Multi-diagonal faults are considered in this paper, thus more exploitable faulty ciphertexts can be gathered compared with the previous model. Multi-fault analysis is introduced...
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