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An 8-bit 1-GS/s hybrid analog-to-digital converter (ADC) for high-speed low-power applications is introduced. It has a subranging architecture with a 3-bit flash ADC as a first stage and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. In each channel, a merged sample-and-hold and capacitive digital-to-analog converter (SHDAC) performs...
A clock generation system for a 1GS/s 8-bit subranging time-interleaved analog-to-digital converter (ADC) is introduced. General timing considerations for time-interleaved ADCs are reviewed prior to describing the design methodology for a prototype ADC. This hybrid ADC architecture contains four time-interleaved combined sample-and-hold and capacitive digital-to-analog converter (SHDAC) circuits as...
Time Interleaved ADCs (TIADCs) are a good solution to implement high sampling rate converters at a moderate hardware cost. However, they suffer from mismatches between the ADC channels such as offset, gain, timing skew and possibly bandwidth mismatches. These mismatches have to be corrected in order to get sufficient performances from the converter. This paper presents the classical calibration methods...
Today's applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates and high resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, this structure suffers from mismatches between the sub-converters, which cause errors on the output signal, and more significantly,...
Positioning services are increasingly used for applications such as navigation, advertising and social media. While outdoor navigation based on GPS and/or cellular systems works well, indoor navigation is a much tougher challenge. This paper presents a new indoor positioning method based on Wi-Fi fingerprints, i.e. RSSI measurements from multiple Wi-Fi access points. During an offline phase, fingerprints...
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