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The increasing use of digital signal processors (DSPs) in wireless communications and signal processing necessitates the optimization of compilers to support special hardware features. In this paper, we propose a compiler transformation method for zero overhead loop (ZOL). It supports very long instruction word (VLIW), internal branches and the loops whose iterative times are known at runtime and...
This paper presents SWIFT, a computationally intensive DSP Architecture for communication applications. We introduce the VLIW feature and SIMD capability of SWIFT, and the vector register file, store buffer, multi-banked memories as well. Then, the structure of nine stages pipeline with powerful bypass logics is disclosed. Finally, the hardware implementation of SWIFT is shown. In SWIFT, computation,...
In this paper, we propose a VLIW DSP architecture SWIFT for communication applications. The SWIFT core includes four parallel SIMD datapath. Each VLIW instruction includes up to four sub-instructions. Therefore, computation, data access and control operation can be handled orthogonally to improve computation performance. Then the pipeline structure, register file, and memory structure of SWIFT DSP...
In this paper, a new test data compression technique is proposed. The compression is achieved by reversed leading bits coding together with Huffman coding (RLBC-HC). RLBC-HC fills the don't-care bit with the value of the bit before it at first. Then the test data is divided into codeword segments for pattern matching to generate corresponding symbols. With a proper number of patterns, the number of...
In this paper, a new linear feedback shift register (LFSR) structure for scan-based built-in self-test (BIST), which has at least two characteristic polynomials, is proposed. Multiple polynomials are utilized to generate the pattern sequences for feeding the scan chain of the circuit under test in pseudorandom testing phase. Using the proposed LFSR, same or even better fault coverage can be achieved...
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