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Microstructure variation with post-patterning dielectric aspect ratio (AR) and post-plating annealing temperature has been investigated in Cu narrow wires. As compared to the conventional annealing at 100 ◦C for a feature AR of 2.6, both elevated temperature anneals and reduced AR structures modulated Cu microstructure, which then resulted in a reduced rate of electrical resistivity increase with...
Adhesion tests, parametric measurements, and reliability evaluations of an in-situ pre-liner dielectric nitridation process prior to pure Ta liner deposition were carried out, to evaluate the feasibility of reducing via resistance in BEOL Cu/low-k interconnects. Replacing TaN/Ta with Ta in the conventional liner stack reduces Cu via resistance, while the nitridation treatment maintains Cu interconnect...
Multi-layer SiNO barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCN and SiN barrier films used at previous technology nodes. Combining SiCN with multi-layer SiNO barrier film provides robust Cu and O barrier properties at film thickness of ∼10–14 nm. SiNO layers in the bi-layer film help lower the dielectric constant and hence provide...
Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co...
A cost effective 28nm CMOS Interconnect technology is presented for 28nm node high performance and low power applications. Full entitlement of ultra low-k (ULK) inter-level dielectric is enabled. Copper wiring levels can be combined up to a total of 11 levels. The inter-level dielectric was optimized for low k-value and high strength. The feature profiles were optimized to enable defect-free metallization...
A fully planarized two-level-metal structure has been successfully fabricated at 0.5 μm groundrules with the use of X-ray lithography at all processing levels. A 0.5-μm minimum feature size was required for all levels, including the second-level metal. Planarized PECVD oxide and PECVD nitride were employed as dual dielectric layers below M1 and M2. Chemical vapor deposition (CVD) W studs...
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