This paper presents architecture for a fused floating point three term adder unit. The fused or merge technique is described in this paper because in a fused technique three term addition is done in single unit. The purpose of doing this is to reduce delay, area as compared to traditional addition method. Several optimization techniques are used to reduce delay. The proposed design is implemented and simulated on Xilinx vertex 6 FPGA device. This paper describes the optimization of fused floating point three term adder in terms of area, delay.