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In this paper an efficient fused three operand floating point add-subtract unit is designed using Binary Signed Digit (BSD) adder. BSD adder-subtractor improves overall speed of addition due to its carry limited operation. BSD adder delay reduces by 28% and 17% compared to carry save adder (CSA) and ripple carry adder (RCA) respectively. Three operand adder performs two additions in a single unit...
Signed binary multiplication is the essential part of all digital processing needs. The digital processing is inseparable part in microprocessor, microcontroller, digital image processing, data manipulation, etc. In this paper, a method to generate the partial products which are generated in the multiplication process is being proposed, in order to reduce the computational efforts in the multiplication...
This paper presents architecture for a fused floating point three term adder unit. The fused or merge technique is described in this paper because in a fused technique three term addition is done in single unit. The purpose of doing this is to reduce delay, area as compared to traditional addition method. Several optimization techniques are used to reduce delay. The proposed design is implemented...
In this paper, a three operand floating point adder with reduced delay has been implemented. In this, the internal width which mainly gives the delay has been given compatible with IEEE Std-754. Here for designing three operand floating point adder, Realignment method, which avoid more than one sticky generation, an low cost OR-logic network in the replacement of comparer has been employed, to detect...
As floating point architecture is very hot topic for researchers so challenges are always there to design the efficient Floating point architecture. Out of other operations, Floating point multiplication is the most commonly used operation and it requires the multiplication of the mantissa of Floating point numbers. This paper presents the highly efficient 64 bit multiplier for the mantissa calculation...
Digital signal processing algorithms are implemented using fixed point arithmetic due to expected area and power savings. However, the recent research shows that floating point arithmetic can be used by using the reduced precision format instead of standard IEEE floating point format which will avoid the algorithm design and implementation difficulties occurs in fixed point arithmetic. In this paper,...
This paper presents a fast single precision floating point multiplier. In most of the industrial areas like DSP, image processing, microprocessor, it is needed to do arithmetic operations very fast with greater accuracy and multiplier is widely used in these application areas. So we decide to increase the speed of floating point multiplication unit. To improve the speed of multiplier we minimize the...
This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP-C) processors. The design is implemented and simulated by targeting Xilinx vertex 5 FPGA device. This paper describes the optimization of fused floating point modules...
This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP-C) processors. The design is implemented and simulated by targeting Xilinx vertex 5 FPGA device. This paper describes the optimization of fused floating point modules...
In this paper Flash ADC is designed using improved PSR digital comparator approach for effective speed and power improvement by eliminating complete resistive ladder circuit. Comparator used in this design is with improved power supply rejection ratio compared to TIQ (threshold inverter quantization) comparators. Additional clocking strategy is incorporated which leads to elimination of sample and...
Here we have proposed a design of Peak Detector and Sub-Flash architecture for adaptive Resolution ADC in 90nm Technology. The control circuits are developed for Adaptive Resolution for Flash ADC. Peak detector circuits will consist of peak detector for variable resolution and sub-flash architecture for reconfigurability. The voltages from the Bias block are used to provide a control voltage for Peak...
In this paper Flash ADC (FADC) is Implemented in 0.18 µm technology using CMOS Inverter based Threshold inverter Quantized (TIQ) comparator for effective speed and power improvement by eliminating complete resistive ladder circuit. Thermometer to binary decoder with low power consumption, less area & short critical path is selected for the design of low power high speed FADC. Presence of bubble...
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