With recent advances and demands for data storage, new architectures for data controller chips are picking pace. Accordingly, the test methodologies for such chips are also becoming crucial since the large shipping volumes of those chips demand very few field returns. Along with the advances there is a need for a robust test strategy with some novel techniques which can be enabled to test the SOC effectively and allow shorter time to market. This paper highlights the test strategies developed to test typical storage chips showing the methodology improvements over generations of designs taking into account the learnings from field returns.