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With recent advances and demands for data storage, new architectures for data controller chips are picking pace. Accordingly, the test methodologies for such chips are also becoming crucial since the large shipping volumes of those chips demand very few field returns. Along with the advances there is a need for a robust test strategy with some novel techniques which can be enabled to test the SOC...
Clock architecture in digital designs goes throughan iterative cycle of timing analysis, routing and placement andfixes to meet timing. At a higher level, each of these steps must bedone in different scenarios for example: test mode and functionalmode. There can be multiple test modes also. There can be manyfunctional clocks in the design adding to the complexity. Eachfunctional clock can spread in...
Memories from the Library vendor come as a hard macro in the design. With the increased focus on meeting timing requirements, memories are provided in an integrated form from vendor. These integrated memory hard macros not only consist of SRAM read-write behavior but also comprise of scan chains and bypass logic around SRAM. This bypass logic consists of shadow cells which are already stitched into...
A repairable memory cell consists of repair logic and a memory repair register (MRR) which holds the signature for memory repair. Every time a repairable memory is powered on, the memory repair register is programmed by transferring the memory repair signature from a nonvolatile memory such an EPROM into MRR. During repair signature programming, the MRR of all memories in the design are wired together...
This work presents a method to measure the frequency of an on-chip test clock in relation to a reference clock. Frequency measurement is accomplished by counting pulses of both test and reference clocks, albeit adjusting the reference clock pulse count to estimate the number of pulses that the test clock is expected to see. The proposed method places no constraints on the frequency relationship between...
Low-power testing has become a need for modern designs due to rapid increasing of power density with further shrinking of feature size into nanoscale designs. In spite of low-power design efforts and low-power ATPG adopted in common test flows, excessive power dissipation and instant peak current cannot be necessarily avoided during test application. There is a need for fast peak power detection for...
This work presents an universal, lossless, linear, low complexity data transformation algorithm based on the sampling theorem that significantly reduces the complexity of operations in data processing systems. While many lossy and lossless compression methods are in existence, the data compressed by such methods cannot be directly processed by signal processing systems without decompression due to...
This work presents a variation of the non restoring division algorithm that has been optimized for low power consumption. The approach uses the value of the partial remainder at any stage in the computation to predict the quotient bits for a certain number of steps thereby allowing an equal number of computation steps to be skipped. This results in a significant reduction in switching activity in...
Use of Nand Flash memory in storage devices is increasing at an exponential rate. As the technology feature size shrink, the reliability and endurance for the Nand device reduces. Currently Nand devices can have more than 258Gb cells. Testing such devices is not a trivial proposition. In this presentation we will discuss the failure modes for Nand flash, the test methods used and the challenges that...
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