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Low-power becomes a critical issue for modern VLSI designs. Unified Power Format (UPF) was invented for power management and enables the low-power design flow. In the UPF specification, controlling cells (including isolation cells, level shifter and retention cells) need to be placed properly to prevent unpredictable errors. Therefore, many commercial EDA tools support to examine the correctness of...
IOT has seen countless potential applications that can improve our lives dramatically, but after years of efforts by numerous companies and organizations, the beautiful dreams are yet to be realized. The main obstacles are cost and energy consumption constraints of the devices and systems, which still cannot be contained. As a step forward in improving the reliability and reducing the cost and energy...
In this work we propose a hybrid concurrent error detection (CED) scheme that combines the implication-based method with the parity check method. The parity check method is easy to implement and has high probability of detecting errors, while the implication-based method has high flexibility to be easily integrated with other CED methods for improidng the probability of detecting errors. In addition,...
This paper presents a physical-aware diagnosis technique for failing dies with multiple interconnect defects, including open and bridging. Our diagnosis technique considers fault masking/reinforcement and Byzantine effects. We use a section, a piece of interconnect, as the physical-aware diagnosis unit. We adopt the Single Location in a Cluster (SLIC) technique, where sections with similar simulation...
This paper presents the design and implementation of a fault simulator for the TRAnsition-X fault model (TRAX for short) on a graphics processing unit (GPU). Fault dictionaries are an important aspect of on-chip fault detection and diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. The inherent parallelism of the...
This paper proposes low-distortion sinusoidal/two-tone signal generation techniques for analog/mixed-signal IC testing with a digital Automatic Test Equipment (ATE) using only single digital output pin. They provide a rectangular waveform approximated to a single-tone or two-tone with specified harmonics suppression; we can specify multiple harmonics to suppress using digital control, and it is followed...
The run-pause-resume (RPR) debug methodology allows one to pause the normal circuit operations, observe the internal states of flip-flops and then resume the normal operations for further debug process. Data invalidation is a major problem that needs to be addressed when debugging a multiple-clock design with this methodology. This problem occurs when flip-flops in a receiving clock domain capture...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
The accessibility of on-chip embedded infrastructure for test, reconfiguration, or debug poses a serious security problem. Access mechanisms based on IEEE Std 1149.1 (JTAG), and especially reconfigurable scan networks (RSNs), as allowed by IEEE Std 1500, IEEE Std 1149.1-2013, and IEEE Std 1687 (IJTAG), require special care in the design and development. This work studies the threats to trustworthy...
Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the...
The emerging Internet-of-Things (IoT) paradigm creates a new market for very small and cost-sensitive chips. Design costs must be as low as possible in order to be competitive. In this context, the 1-pin test has proven to be a beneficial way to significantly reduce test costs. However, the incorporated signature generation requires an X-free design, which is not always possible (e.g. due to timing...
Embedded power regulators, such as low dropout regulators (LDOs), are generally tested for DC behavior and are rarely characterized dynamically. However, LDO loop dynamics play an important role in the overall behavior of the system. Dynamic characterization of LDOs based directly on LDO specifications requires measurement of output transient response with a step input at various points in the circuit...
This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the...
Simulating/Measuring the jitter tolerance of clock and data recovery (CDR) circuits, and confirming if the associated jitter tolerance meets the required specification for a specified communication standard, is an important consideration for designing/testing high-speed serial link interface circuits. However, conducting such performance evaluations are costly and time-consuming. In this paper, a...
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