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Simulating/Measuring the jitter tolerance of clock and data recovery (CDR) circuits, and confirming if the associated jitter tolerance meets the required specification for a specified communication standard, is an important consideration for designing/testing high-speed serial link interface circuits. However, conducting such performance evaluations are costly and time-consuming. In this paper, a...
This paper presents a novel low power duobinary voltage mode transmitter in 90-nm CMOS process for wireline communication. As a matter of fact, voltage mode transmitters potentially save much more power than current mode transmitters. By adding a medium level, a half supply voltage, to conventional NRZ voltage mode transmitters, duobinary coding can simply be achieved. Post-layout simulation demonstrates...
A continuous-rate clock and data recovery (CDR) circuit with unbounded frequency detection mechanism is proposed herein. The unbounded frequency detection mechanism combines the digital quadricorrelator frequency detection and subharmonic tone frequency detection techniques. By adopting the unbounded frequency detector, this reference-less CDR circuit has no locking range limitation and provides an...
This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing...
This paper presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency for digital-based clock and data recovery circuits (CDRs). By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique for constant system bandwidth is...
This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area...
This paper presents a 3.2 Gb/s low-power clock and data recovery (CDR). The improved architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared between frequency presetting and data recovery modes is presented to remove the LC-tank voltage-controlled oscillator in a cascaded CDR. Moreover, using the proposed active inductive loading technique instead of the on-chip inductor...
This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M...
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